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| this is information on a product in full production. september 2013 doc id 14723 rev 9 1/112 1 spc560p44l3, spc560p44l5 spc560p50l3, spc560p50l5 32-bit power architecture ? based mcu with 576 kb flash memory and 40 kb sram for automotive chassis and safety applications datasheet ? production data features 64 mhz, single issue, 32-bit cpu core complex (e200z0h) ? compliant with power architecture ? embedded category ? variable length encoding (vle) memory organization ? up to 512 kb on-chip code flash memory with ecc and erase/program controller ? additional 64 (4 16) kb on-chip data flash memory with ecc for eeprom emulation ? up to 40 kb on-chip sram with ecc fail safe protection ? programmable watchdog timer ? non-maskable interrupt ? fault collection unit nexus l2+ interface interrupts ? 16-channel edma controller ? 16 priority level controller general purpose i/os individually programmable as input, output or special function 2 general purpose etimer units ? 6 timers each with up/down count capabilities ? 16-bit resolution, cascadable counters ? quadrature decode with rotation direction flag ? double buffer input capture and output compare communications interfaces ? 2 linflex channels (lin 2.1) ? 4 dspi channels with automatic chip select generation ? 1 flexcan interface (2.0b active) with 32 message objects ? 1 safety port based on flexcan with 32 message objects and up to 7.5 mbit/s capability; usable as second can when not used as safety port ? 1 flexray? module (v2.1) with selectable dual or single channel support, 32 message objects and up to 10 mbit/s (512 kb device only) two 10-bit analog-to-digital converters (adc) ? 2 11 input channels, + 4 shared channels ? conversion time < 1 s including sampling time at full precision ? programmable adc cross triggering unit (ctu) ? 4 analog watchdogs with interrupt capability on-chip can/uart bootstrap loader with boot assist module (bam) 1 flexpwm unit: 8 complementary or independent outputs with adc synchronization signals table 1. device summary package part number 448 kb flash 576 kb flash lqfp144 spc560p44l5 spc560p50l5 lqfp100 spc560p44l3 spc560p50l3 lqfp100 (14 x 14 x 1.4 mm) lqfp144 (20 x 20 x 1.4 mm) www.st.com
contents spc560p44lx, spc560p50lx 2/112 doc id 14723 rev 9 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.1 high performance e200z0 core processor . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.3 enhanced direct memory access (edma) . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.4 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.5 static random access memory (sram) . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.6 interrupt controller (intc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.7 system status and configuration module (sscm) . . . . . . . . . . . . . . . . . 16 1.5.8 system clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.9 frequency-modulated phase-locked loop (fmpll) . . . . . . . . . . . . . . . . 17 1.5.10 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.11 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.12 periodic interrupt timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.13 system timer module (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.14 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.15 fault collection unit (fcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.16 system integration unit ? lite (siul) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.17 boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.18 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.19 peripheral bridge (pbridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.20 controller area network (flexcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.21 safety port (flexcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.22 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.23 serial communication interface module (linflex) . . . . . . . . . . . . . . . . . 22 1.5.24 deserial serial peripheral interface (dspi) . . . . . . . . . . . . . . . . . . . . . . 23 1.5.25 pulse width modulator (flexpwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.26 etimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.27 analog-to-digital converter (adc) module . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.28 cross triggering unit (ctu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 spc560p44lx, spc560p50lx contents doc id 14723 rev 9 3/112 1.5.29 nexus development interface (ndi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.30 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.31 ieee 1149.1 jtag controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.32 on-chip voltage regulator (vreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 29 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.1 power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.2 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.3 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.5.1 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.5.2 general notes for specifications at maximum junction temperature . . . 57 3.6 electromagnetic interference (emi) characteristics . . . . . . . . . . . . . . . . . 59 3.7 electrostatic discharge (esd) characteristics . . . . . . . . . . . . . . . . . . . . . 59 3.8 power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 59 3.8.1 voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 59 3.8.2 voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63 3.9 power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.10 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.10.1 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.10.2 dc electrical characteristics (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.10.3 dc electrical characteristics (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.10.4 input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . 69 3.10.5 i/o pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.11 main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.12 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.13 16 mhz rc oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 78 contents spc560p44lx, spc560p50lx 4/112 doc id 14723 rev 9 3.14 analog-to-digital converter (adc) electrical characteristics . . . . . . . . . . . 78 3.14.1 input impedance and adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.14.2 adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.15 flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.16 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.16.1 pad ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.17 ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.17.1 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.17.2 ieee 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.17.3 nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.17.4 external interrupt timing (irq pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.17.5 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.2.1 lqfp144 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.2.2 lqfp100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . 103 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 appendix a abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 spc560p44lx, spc560p50lx list of tables doc id 14723 rev 9 5/112 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. spc560p44lx, spc560p50lx device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. spc560p44lx, spc560p50lx device configuration differences . . . . . . . . . . . . . . . . . . . . . 8 table 4. spc560p44lx, spc560p50lx series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6. system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7. pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 8. parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 10. recommended operating conditions (5.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 11. recommended operating conditions (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 12. thermal characteristics for 144-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 13. thermal characteristics for 100-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 14. emi testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 15. esd ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 16. approved npn ballast components (configuration with resistor on base) . . . . . . . . . . . . . 60 table 17. voltage regulator electrical characteristics (configuration with resistor on base) . . . . . . . . 61 table 18. voltage regulator electrical characteristics (configuration without resistor on base) . . . . . 62 table 19. low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 20. pad3v5v field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 21. dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) . . . . . . . . . . . . . . . . . . . . . 66 table 22. supply current (5.0 v, nvusro[pad3v5v] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 23. dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) . . . . . . . . . . . . . . . . . . . . . 67 table 24. supply current (3.3 v, nvusro[pad3v5v] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 25. i/o supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 26. i/o weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 27. i/o consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 28. main oscillator output electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) . . . . . . . 75 table 29. main oscillator output electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) . . . . . . . 76 table 30. input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 31. fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 32. 16 mhz rc oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 33. adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 34. program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 35. flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 36. flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 37. output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 38. reset electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 39. jtag pin ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 40. nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 41. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 42. dspi timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 43. lqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 44. lqfp100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 45. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 46. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 list of figures spc560p44lx, spc560p50lx 6/112 doc id 14723 rev 9 list of figures figure 1. spc560p44lx, spc560p50lx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. 144-pin lqfp pinout ? full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . 29 figure 3. 100-pin lqfp pinout ? airbag configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 4. 100-pin lqfp pinout ? full featured configuration (top view) . . . . . . . . . . . . . . . . . . . . . . 31 figure 5. power supplies constraints (?0.3 v v dd_hv_iox 6.0 v). . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 6. independent adc supply (?0.3 v v dd_hv_reg 6.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 7. power supplies constraints (3.0 v v dd_hv_iox 5.5 v). . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 8. independent adc supply (3.0 v v dd_hv_reg 5.5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 9. configuration with resistor on base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 10. configuration without resistor on base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11. power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 12. power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 13. brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 14. input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 15. adc characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 16. input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 17. transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 18. spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 19. pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 20. start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 21. noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 22. jtag test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 23. jtag test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 24. jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 25. nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 26. nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 figure 27. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 28. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 29. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 30. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 31. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 32. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 33. dspi modified transfer format timing ? master, cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 34. dspi modified transfer format timing ? master, cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 35. dspi modified transfer format timing ? slave, cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 36. dspi modified transfer format timing ? slave, cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 37. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 00 figure 38. lqfp144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 39. lqfp100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 40. commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 05 spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 7/112 1 introduction 1.1 document overview this document provides electrical specifications, pin assignments, and package diagrams for the spc560p44/50 series of microcontroller units (mcus). it also describes the device features and highlights important electrical and physical characteristics. for functional characteristics, refer to the device reference manual. 1.2 description this 32-bit system-on-chip (soc) automotive microcontroller family is the latest achievement in integrated automotive application controllers. it belongs to an expanding range of automotive-focused products designed to address chassis applications? specifically, electrical hydraulic power steering (ehps) and electric power steering (eps)? as well as airbag applications. this family is one of a series of next-generation integrated automotive microcontrollers based on the power architecture technology. the advanced and cost-efficient host processor core of this automotive controller family complies with the power architecture embedded category. it operates at speeds of up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. 1.3 device comparison ta ble 2 provides a summary of different members of the spc560p44lx, spc560p50lx family and their features?relative to full-featured version?to enable a comparison among the family members and an understanding of the range of functionality offered within this family. table 2. spc560p44lx, spc560p50lx device comparison feature spc560p44 spc560p50 code flash memory (with ecc) 384 kb 512 kb data flash memory / ee option (with ecc) 64 kb sram (with ecc) 36 kb 40 kb processor core 32-bit e200z0h instruction set vle (variable length encoding) cpu performance 0?64 mhz fmpll (frequency-modulated phase-locked loop) module 2 intc (interrupt controller) channels 147 pit (periodic interrupt timer) 1 (includes four 32-bit timers) introduction spc560p44lx, spc560p50lx 8/112 doc id 14723 rev 9 spc560p44lx, spc560p50lx is available in two configurations having different features: full-featured and airbag. ta ble 3 shows the main differences between the two versions. edma (enhanced direct memory access) channels 16 flexray yes (1) flexcan (controller area network) 2 (2),(3) safety port yes (via second flexcan module) fcu (fault collection unit) yes ctu (cross triggering unit) yes etimer 2 (16-bit, 6 channels) flexpwm (pulse-width modulation) channels 8 (capturing on x-channels) adc (analog-to-digital converter) 2 (10-bit, 15-channel (4) ) linflex 2 dspi (deserial serial peripheral interface) 4 crc (cyclic redundancy check) unit yes jtag controller yes nexus port controller (npc) yes (level 2+) supply digital power supply (5) 3.3 v or 5 v single supply with external transistor analog power supply 3.3 v or 5 v internal rc oscillator 16 mhz external crystal oscillator 4?40 mhz packages lqfp100 lqfp144 temperature standard ambient temperature ?40 to 125 c 1. 32 message buffers, selectable single or dual channel support 2. each flexcan module has 32 message buffers. 3. one flexcan module can act as a safety port with a bit rate as high as 7.5 mbit/s. 4. four channels shared between the two adcs 5. the different supply voltages vary according to the part number ordered. table 2. spc560p44lx, spc560p50lx device comparison (continued) feature spc560p44 spc560p50 table 3. spc560p44lx, spc560p50lx device configuration differences feature full-featured airbag ctu (cross triggering unit) yes no flexpwm yes no spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 9/112 1.4 block diagram figure 1 shows a top-level block diagram of the spc560p44lx, spc560p50lx mcu. flexray yes no fmpll (frequency-modulated phase-locked loop) module 2 (one fmpll, one for flexray) 1 (only fmpll) table 3. spc560p44lx, spc560p50lx device configuration differences (continued) feature full-featured airbag introduction spc560p44lx, spc560p50lx 10/112 doc id 14723 rev 9 figure 1. spc560p44lx, spc560p50lx block diagram e200z0 core 32-bit general purpose registers special purpose registers integer execution unit exception handler variable length encoded instructions instruction unit load/store unit branch prediction unit jtag 1.2 v regulator control xosc 16 mhz rc oscillator fmpll_0 (system) nexus port controller interrupt controller edma 16 channels master master instruction 32-bit master data 32-bit sram (with ecc) slave slave crossbar switch (xbar, amba 2.0 v6 ahb) peripheral bridge fcu legend: adc analog-to-digital converter bam boot assist module crc cyclic redundancy check ctu cross triggering unit dspi deserial serial peripheral interface ecsm error correction status module edma enhanced direct memory access etimer enhanced timer fcu fault collection unit flash flash memory flexcan controller area network flexpwm flexible pulse width modulation fmpll frequency-modulated phase-locked loop intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module pit periodic interrupt timer siul system integration unit lite sram static random-access memory sscm system status and configuration module stm system timer module swt software watchdog timer wkpu wakeup unit xosc external oscillator xbar crossbar switch slave external ballast code flash (with ecc) data flash (with ecc) nexus 2+ edma 16 channels flexpwm ctu 4 2 dspi 2 flexcan linflex safety port pit stm swt mc_rgm mc_cgm mc_me bam siul etimer (6 ch) fmpll_1 (flexray, motctrl) flexray sscm 1.2 v rail v reg wkpu crc shared channels channels 10-bit 10-bit 0?10 0?10 channels 11?14 adc_1 adc_0 ecsm spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 11/112 table 4. spc560p44lx, spc560p50lx series block summary block function analog-to-digital converter (adc) multi-channel, 10-bit analog-to-digital converter boot assist module (bam) block of read-only memory containing vle code which is executed according to the boot mode of the device clock generation module (mc_cgm) provides logic and control required for the generation of system and peripheral clocks controller area network (flexcan) supports the standard can communications protocol cross triggering unit (ctu) enables synchronization of adc conversions with a timer event from the emios or from the pit crossbar switch (xbar) supports simultaneous connections between two master ports and three slave ports; supports a 32-bit address bus width and a 32-bit data bus width cyclic redundancy check (crc) crc checksum generator deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ? n ? programmable channels enhanced timer (etimer) provides enhanced programmable up/down modulo counting error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes external oscillator (xosc) provides an output clock used as input reference for fmpll_0 or as reference clock for specific modules depending on system needs fault collection unit (fcu) provides functional safety to the device flash memory provides non-volatile storage for program code, constants and variables frequency-modulated phase- locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with minimum load on cpu mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications periodic interrupt timer (pit) produces periodic interrupts and triggers peripheral bridge (pbridge) interface between the system bus and on-chip peripherals power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu introduction spc560p44lx, spc560p50lx 12/112 doc id 14723 rev 9 pulse width modulator (flexpwm) contains four pwm submodules, each of which is capable of controlling a single half-bridge power stage and two fault input channels reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device static random-access memory (sram) provides storage for program code, constants, and variables system integration unit lite (siul) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system status and configuration module (sscm) provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar (1) and operating system tasks system watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) supports up to 18 external sources that can generate interrupts or wakeup events, 1 of which can cause non-maskable interrupt requests or wakeup events 1. autosar: automotive open system architecture (see www.autosar.org) table 4. spc560p44lx, spc560p50lx series block summary (continued) block function spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 13/112 1.5 feature details 1.5.1 high performance e200z0 core processor the e200z0 power architecture core provides the following features: high performance e200z0 core processor for managing peripherals and interrupts single issue 4-stage pipeline in-order execution 32-bit power architecture cpu harvard architecture variable length encoding (vle), allowing mixed 16-bit and 32-bit instructions ? results in smaller code size footprint ? minimizes impact on performance branch processing acceleration using lookahead instruction buffer load/store unit ? 1 cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles thirty-two 32-bit general purpose registers (gprs) separate instruction bus and load/store bus harvard architecture hardware vectored interrupt support reservation instructions for implementing read-modify-write constructs long cycle time instructions, except for guarded loads, do not increase interrupt latency extensive system development support through nexus debug port non-maskable interrupt support 1.5.2 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 32-bit data bus width. the crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers must be an instruction fetch from internal flash memory. if a slave port is simultaneously requested by more than one master port, arbitration logic will select the higher priority master and grant it ownership of the slave port. all other masters requesting that slave port will be stalled until the higher priority master completes its transactions. requesting masters will be treated with equal priority and will be granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access. introduction spc560p44lx, spc560p50lx 14/112 doc id 14723 rev 9 the crossbar provides the following features: 4 master ports: ? e200z0 core complex instruction port ? e200z0 core complex load/store data port ?edma ?flexray 3 slave ports: ? flash memory (code flash and data flash) ?sram ? peripheral bridge 32-bit internal address, 32-bit internal data paths fixed priority arbitration based on port master temporary dynamic priority elevation of masters 1.5.3 enhanced direct memory access (edma) the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is utilized to minimize the overall block size. the edma module provides the following features: 16 channels support independent 8, 16 or 32-bit single value or block transfers supports variable sized queues and circular queues source and destination address registers are independently configured to either post- increment or to remain constant each transfer is initiated by a peripheral, cpu, or edma channel request each edma channel can optionally send an interrupt request to the cpu on completion of a single value or block transfer dma transfers possible between system memories, dspis, adc, flexpwm, etimer and ctu programmable dma channel multiplexer for assignment of any dma source to any available dma channel with as many as 30 request sources edma abort operation through software 1.5.4 flash memory the spc560p44lx, spc560p50lx provides as much as 576 kb of programmable, non- volatile, flash memory. the non-volatile memory (nvm) can be used for instruction and/or data storage. the flash memory module interfaces the system bus to a dedicated flash memory array controller. it supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. the module contains four 128-bit wide prefetch buffers. prefetch buffer hits allow no-wait responses. normal flash memory array accesses are registered and are forwarded to the system bus on the following cycle, incurring two wait-states. spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 15/112 the flash memory module provides the following features: as much as 576 kb flash memory ? 8 blocks (32 kb + 216 kb + 32 kb + 32 kb + 3128 kb) code flash ? 4 blocks (16 kb + 16 kb + 16 kb + 16 kb) data flash ? full read while write (rww) capability between code and data flash four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to prefetch code or data or both) typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page buffer miss at 64 mhz hardware managed flash memory writes handled by 32-bit risc krypton engine hardware and software configurable read and write access protections on a per-master basis configurable access timing allowing use in a wide range of system frequencies multiple-mapping support and mapping-based block access timing (up to 31 additional cycles) allowing use for emulation of other memory types. software programmable block program/erase restriction control erase of selected block(s) read page sizes ? code flash memory: 128 bits (4 words) ? data flash memory: 32 bits (1 word) ecc with single-bit correction, double-bit detection for data integrity ? code flash memory: 64-bit ecc ? data flash memory: 64-bit ecc embedded hardware program and erase algorithm erase suspend, program suspend and erase-suspended program censorship protection scheme to prevent flash memory content visibility hardware support for eeprom emulation 1.5.5 static random access memory (sram) the spc560p44lx, spc560p50lx sram module provides up to 40 kb of general-purpose memory. the sram module provides the following features: supports read/write accesses mapped to the sram from any master up to 40 kb general purpose sram supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory typical sram access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8- and 16-bit writes if back to back with a read to same memory block 1.5.6 interrupt controller (intc) the interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. the intc handles 147 selectable-priority interrupt sources. introduction spc560p44lx, spc560p50lx 16/112 doc id 14723 rev 9 for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr has to be executed. it also provides a wide number of priorities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. when multiple tasks share a resource, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol (pcp) for coherent accesses. by providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the same resource can not preempt each other. the intc provides the following features: unique 9-bit vector for each separate interrupt source 8 software triggerable interrupt sources 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source ability to modify the isr or task priority: modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. 2 external high priority interrupts directly accessing the main core and i/o processor (iop) critical interrupt mechanism 1.5.7 system status and configuration module (sscm) the system status and configuration module (sscm) provides central device functionality. the sscm includes these features: system configuration and status ? memory sizes/status ? device mode and security status ? determine boot vector ? search code flash for bootable sector ?dma status debug status port enable and selection bus and peripheral abort enable/disable 1.5.8 system clocks and clock generation the following list summarizes the system clock and clock generation on the spc560p44lx, spc560p50lx: lock detect circuitry continuously monitors lock status loss of clock (loc) detection for pll outputs programmable output clock divider ( 1, 2, 4, 8) flexpwm module and etimer module can run on an independent clock source on-chip oscillator with automatic level control internal 16 mhz rc oscillator for rapid start-up and safe mode: supports frequency trimming by user application spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 17/112 1.5.9 frequency-modulated phase-locked loop (fmpll) the fmpll allows the user to generate high speed system clocks from a 4?40 mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the pll multiplication factor, output clock divider ratio are all software configurable. the pll has the following major features: input clock frequency: 4?40 mhz maximum output frequency: 64 mhz voltage controlled oscillator (vco)?frequency 256?512 mhz reduced frequency divider (rfd) for reduced frequency operation without forcing the pll to relock frequency-modulated pll ? modulation enabled/disabled through software ? triangle wave modulation programmable modulation depth (0.25% to 4% deviation from center frequency): programmable modulation frequency dependent on reference frequency self-clocked mode (scm) operation 1.5.10 main oscillator the main oscillator provides these features: input frequency range: 4?40 mhz crystal input mode or oscillator input mode pll reference 1.5.11 internal rc oscillator this device has an rc ladder phase-shift oscillator. the architecture uses constant current charging of a capacitor. the voltage at the capacitor is compared by the stable bandgap reference voltage. the rc oscillator provides these features: nominal frequency 16 mhz 5% variation over voltage and temperature after process trim clock output of the rc oscillator serves as system clock source in case loss of lock or loss of clock is detected by the pll rc oscillator is used as the default system clock during startup 1.5.12 periodic interrupt timer (pit) the pit module implements these features: 4 general purpose interrupt timers 32-bit counter resolution clocked by system clock frequency each channel can be used as trigger for a dma request introduction spc560p44lx, spc560p50lx 18/112 doc id 14723 rev 9 1.5.13 system timer module (stm) the stm module implements these features: one 32-bit up counter with 8-bit prescaler four 32-bit compare channels independent interrupt source for each channel counter can be stopped in debug mode 1.5.14 software watchdog timer (swt) the swt has the following features: 32-bit time-out register to set the time-out period programmable selection of system or oscillator clock for timer operation programmable selection of window mode or regular servicing programmable selection of reset or interrupt on an initial time-out master access protection hard and soft configuration lock bits reset configuration inputs allow timer to be enabled out of reset 1.5.15 fault collection unit (fcu) the fcu provides an independent fault reporting mechanism even if the cpu is malfunctioning. the fcu module has the following features: fcu status register reporting the device status continuous monitoring of critical fault signals user selection of critical signals from different fault sources inside the device critical fault events trigger 2 external pins (user selected signal protocol) that can be used externally to reset the device and/or other circuitry (for example, safety relay or flexray transceiver) faults are latched into a register 1.5.16 system integration unit ? lite (siul) the spc560p44lx, spc560p50lx siul controls mcu pad configuration, external interrupt, general purpose i/o (gpio), and internal peripheral multiplexing. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 19/112 the siu provides the following features: centralized general purpose input output (gpio) control of as many as 80 input/output pins and 26 analog input-only pads (package dependent) all gpio pins can be independently configured to support pull-up, pull down, or no pull reading and writing to gpio supported both as individual pins and 16-bit wide ports all peripheral pins (except adc channels) can be alternatively configured as both general purpose input or output pins adc channels support alternative configuration as general purpose inputs direct readback of the pin value is supported on all pins through the siul configurable digital input filter that can be applied to some general purpose input pins for noise elimination: as many as 4 internal functions can be multiplexed onto 1 pin 1.5.17 boot and censorship different booting modes are available in the spc560p44lx, spc560p50lx: booting from internal flash memory and booting via a serial link. the default booting scheme uses the internal flash memory (an internal pull-down is used to select this mode). optionally, the user can boot via flexcan or linflex (using the boot assist module software). a censorship scheme is provided to protect the content of the flash memory and offer increased security for the entire device. a password mechanism is designed to grant the legitimate user access to the non-volatile memory. boot assist module (bam) the bam is a block of read-only one-time programmed memory and is identical for all spc560pxx devices that are based on the e200z0h core. the bam program is executed every time the device is powered on if the alternate boot mode has been selected by the user. the bam provides the following features: serial bootloading via flexcan or linflex ability to accept a password via the used serial communication channel to grant the legitimate user access to the non-volatile memory 1.5.18 error correction status module (ecsm) the ecsm provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes, and information on platform memory errors reported by error-correcting codes and/or generic access error information for certain processor cores. the error correction status module supports a number of miscellaneous control functions for the platform. the ecsm includes these features: registers for capturing information on platform memory errors if error-correcting codes (ecc) are implemented for test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the spc560p44lx, spc560p50lx. introduction spc560p44lx, spc560p50lx 20/112 doc id 14723 rev 9 the sources of the ecc errors are: flash memory sram 1.5.19 peripheral bridge (pbridge) the pbridge implements the following features: duplicated periphery master access privilege level per peripheral (per master: read access enable; write access enable) write buffering for peripherals checker applied on pbridge output toward periphery byte endianess swap capability 1.5.20 controller area network (flexcan) the spc560p44lx, spc560p50lx mcu contains one controller area network (flexcan) module. this module is a communication controller implementing the can protocol according to bosch specification version 2.0b. the can protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real- time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module contains 32 message buffers. spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 21/112 the flexcan module provides the following features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? up to 8-bytes data length ? programmable bit rate up to 1 mbit/s 32 message buffers of up to 8-bytes data length each message buffer configurable as rx or tx, all supporting standard and extended messages programmable loop-back mode supporting self-test operation 3 programmable mask registers programmable transmit-first scheme: lowest id or lowest buffer number time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts independent of the transmission medium (an external transceiver is assumed) high immunity to emi short latency time due to an arbitration scheme for high-priority messages transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to message id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a six-entry receive fifo ? 8 programmable acceptance filters for receive fifo programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter 1.5.21 safety port (flexcan) the spc560p44lx, spc560p50lx mcu has a second can controller synthesized to run at high bit rates to be used as a safety port. the can module of the safety port provides the following features: identical to the flexcan module bit rate as fast as 7.5 mbit/s at 60 mhz cpu clock using direct connection between can modules (no physical transceiver required) 32 message buffers of up to 8 bytes data length can be used as a second independent can module introduction spc560p44lx, spc560p50lx 22/112 doc id 14723 rev 9 1.5.22 flexray the flexray module provides the following features: full implementation of flexray protocol specification 2.1 32 configurable message buffers can be handled dual channel or single channel mode of operation, each as fast as 10 mbit/s data rate message buffers configurable as tx, rx or rxfifo message buffer size configurable message filtering for all message buffers based on frameid, cycle count and message id programmable acceptance filters for rxfifo message buffers 1.5.23 serial communication interface module (linflex) the linflex (local interconnect network flexible) on the spc560p44lx, spc560p50lx features the following: supports lin master mode, lin slave mode and uart mode lin state machine compliant to lin1.3, 2.0, and 2.1 specifications handles lin frame transmission and reception without cpu intervention lin features ? autonomous lin frame handling ? message buffer to store identifier and as much as 8 data bytes ? supports message length as long as 64 bytes ? detection and flagging of lin errors (sync field, delimiter, id parity, bit framing, checksum, and time-out) ? classic or extended checksum calculation ? configurable break duration as long as 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features: loop back; self test; lin bus stuck dominant detection ? interrupt-driven operation with 16 interrupt sources lin slave mode features ? autonomous lin header handling ? autonomous lin response handling uart mode ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt-driven operation with four interrupt sources ? separate transmitter and receiver cpu interrupt sources ? 16-bit programmable baud-rate modulus counter and 16-bit fractional ? 2 receiver wake-up methods spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 23/112 1.5.24 deserial serial peripheral interface (dspi) the deserial serial peripheral interface (dspi) module provides a synchronous serial interface for communication between the spc560p44lx, spc560p50lx mcu and external devices. the dspi modules provide these features: full duplex, synchronous transfers master or slave operation programmable master bit rates programmable clock polarity and phase end-of-transmission interrupt flag programmable transfer baud rate programmable data frames from 4 to 16 bits up to 20 chip select lines available ?8 on dspi_0 ? 4 each on dspi_1, dspi_2 and dspi_3 8 clock and transfer attributes registers chip select strobe available as alternate function on one of the chip select pins for deglitching fifos for buffering as many as 5 transfers on the transmit and receive side queueing operation possible through use of the edma general purpose i/o functionality on pins when not used for spi 1.5.25 pulse width modulator (flexpwm) the pulse width modulator module (pwm) contains four pwm submodules, each capable of controlling a single half-bridge power stage. there are also four fault channels. this pwm is capable of controlling most motor types: ac induction motors (acim), permanent magnet ac motors (pmac), both brushless (bldc) and brush dc motors (bdc), switched (srm) and variable reluctance motors (vrm), and stepper motors. introduction spc560p44lx, spc560p50lx 24/112 doc id 14723 rev 9 the flexpwm block implements the following features: 16-bit resolution for center, edge-aligned, and asymmetrical pwms maximum operating clock frequency of 120 mhz pwm outputs can operate as complementary pairs or independent channels can accept signed numbers for pwm generation independent control of both edges of each pwm output synchronization to external hardware or other pwm supported double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability multiple adc trigger events can be generated per pwm cycle via hardware write protection for critical registers fault inputs can be assigned to control multiple pwm outputs programmable filters for fault inputs independently programmable pwm output polarity independent top and bottom deadtime insertion each complementary pair can operate with its own pwm frequency and deadtime values individual software-control for each pwm output all outputs can be programmed to change simultaneously via a ?force out? event pwmx pin can optionally output a third pwm signal from each submodule channels not used for pwm generation can be used for buffered output compare functions channels not used for pwm generation can be used for input capture functions enhanced dual-edge capture functionality edma support with automatic reload 2 fault inputs capture capability for pwma, pwmb, and pwmx channels not supported spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 25/112 1.5.26 etimer the spc560p44lx, spc560p50lx includes two etimer modules. each module provides six 16-bit general purpose up/down timer/counter units with the following features: maximum operating clock frequency of 120 mhz individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0?100% pulse measurement ? rotation direction flag (quad decoder mode) maximum count rate ? external event counting: max. count rate = peripheral clock/2 ? internal clock counting: max. count rate = peripheral clock counters are: ? cascadable ? preloadable programmable count modulo quadrature decode capabilities counters can share available input pins count once or repeatedly pins available as gpio when timer functionality not in use 1.5.27 analog-to-digital converter (adc) module the adc module provides the following features: analog part: 2 on-chip ad converters ? 10-bit ad resolution ? 1 sample and hold unit per adc ? conversion time, including sampling time, less than 1 s (at full precision) ? typical sampling time is 150 ns min. (at full precision) ? differential non-linearity error (dnl) 1 lsb ? integral non-linearity error (inl) 1.5 lsb ?tue <3lsb ? single-ended input signal up to 5.0 v ? the adc and its reference can be supplied with a voltage independent from v ddio ? the adc supply can be equal or higher than v ddio ? the adc supply and the adc reference are not independent from each other (they are internally bonded to the same pad) ? sample times of 2 (default), 8, 64, or 128 adc clock cycles introduction spc560p44lx, spc560p50lx 26/112 doc id 14723 rev 9 digital part: 2 13 input channels including 4 channels shared between the 2 converters 4 analog watchdogs comparing adc results against predefined levels (low, high, range) before results are stored in the appropriate adc result location, 2 modes of operation: normal mode or ctu control mode normal mode features ? register-based interface with the cpu: control register, status register, 1 result register per channel ? adc state machine managing 3 request flows: regular command, hardware injected command, software injected command ? selectable priority between software and hardware injected commands ? 4 analog watchdogs comparing adc results against predefined levels (low, high, range) ? dma compatible interface ctu control mode features ? triggered mode only ? 4 independent result queues (2 16 entries, 2 4 entries) ? result alignment circuitry (left justified; right justified) ? 32-bit read mode allows to have channel id on one of the 16-bit part ? dma compatible interfaces 1.5.28 cross triggering unit (ctu) the cross triggering unit allows automatic generation of adc conversion requests on user selected conditions without cpu load during the pwm period and with minimized cpu load for dynamic configuration. it implements the following features: double buffered trigger generation unit with as many as eight independent triggers generated from external triggers trigger generation unit configurable in sequential mode or in triggered mode each trigger can be appropriately delayed to compensate the delay of external low pass filter double buffered global trigger unit allowing etimer synchronization and/or adc command generation double buffered adc command list pointers to minimize adc-trigger unit update double buffered adc conversion command list with as many as 24 adc commands each trigger has the capability to generate consecutive commands adc conversion command allows to control adc channel from each adc, single or synchronous sampling, independent result queue selection 1.5.29 nexus development interface (ndi) the ndi (nexus development interface) block provides real-time development support capabilities for the spc560p44lx, spc560p50lx power architecture based mcu in compliance with the ieee-isto 5001-2003 standard. this development support is supplied for mcus without requiring external address and data pins for internal visibility. the ndi spc560p44lx, spc560p50lx introduction doc id 14723 rev 9 27/112 block is an integration of several individual nexus blocks that are selected to provide the development support interface for this device. the ndi block interfaces to the host processor and internal busses to provide development support as per the ieee-isto 5001- 2003 class 2+ standard. the development support provided includes access to the mcu?s internal memory map and access to the processor?s internal registers during run time. the nexus interface provides the following features: configured via the ieee 1149.1 all nexus port pins operate at v ddio (no dedicated power supply) nexus 2+ features supported ? static debug ? watchpoint messaging ? ownership trace messaging ? program trace messaging ? real time read/write of any internally memory mapped resources through jtag pins ? overrun control, which selects whether to stall before nexus overruns or keep executing and allow overwrite of information ? watchpoint triggering, watchpoint triggers program tracing auxiliary output port ? 4 mdo (message data out) pins ? mcko (message clock out) pin ? 2 mseo (message start/end out) pins ?evto (event out) pin auxiliary input port ?evti (event in) pin 1.5.30 cyclic redundancy check (crc) the crc computing unit is dedicated to the computation of crc off-loading the cpu. the crc module features: support for crc-16-ccitt ( x 25 protocol): ? x 16 + x 12 + x 5 + 1 support for crc-32 (ethernet protocol): ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 zero wait states for each write/read operations to the crc_cfg and crc_inp registers at the maximum frequency 1.5.31 ieee 1149.1 jtag controller the jtag controller (jtagc) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee standard. introduction spc560p44lx, spc560p50lx 28/112 doc id 14723 rev 9 the jtag controller provides the following features: ieee test access port (tap) interface with 4 pins (tdi, tms, tck, tdo) selectable modes of operation include jtagc/debug or normal system operation. a 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ? bypass, idcode, extest, sample, sample/preload a 5-bit instruction register that supports the additional following public instructions: ? access_aux_tap_npc, access_aux_tap_once 3 test data registers: a bypass register, a boundary scan register, and a device identification register. a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry. 1.5.32 on-chip voltage regulator (vreg) the on-chip voltage regulator module provides the following features: uses external npn (negative-positive-negative) transistor regulates external 3.3 v /5.0 v down to 1.2 v for the core logic low voltage detection on the internal 1.2 v and i/o voltage 3.3 v spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 29/112 2 package pinouts and signal descriptions 2.1 package pinouts the lqfp pinouts are shown in the following figures. figure 2. 144-pin lqfp pinout ? full featured configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi a[6] d[1] f[4] f[5] vdd_hv_io0 vss_hv_io0 f[6] mdo[0] a[7] c[4] a[8] c[5] a[5] c[7] c[3] vss_lv_cor0 vdd_lv_cor0 f[7] f[8] vdd_hv_io1 vss_hv_io1 f[9] f[10] f[11] d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_cor3 vdd_lv_cor3 a[4] vpp_test f[12] d[14] g[3] c[14] g[2] c[13] g[4] d[12] g[6] vdd_hv_fl vss_hv_fl d[13] vss_lv_cor1 vdd_lv_cor1 a[3] vdd_hv_io2 vss_hv_io2 tdo tck tms tdi g[5] a[2] g[7] c[12] g[8] c[11] g[9] d[11] g[10] d[10] g[11] a[1] a[0] d[7] g[0] e[1] e[3] c[1] e[4] b[7] e[5] c[2] e[6] b[8] e[7] e[2] vdd_hv_adc0 vss_hv_adc0 b[9] b[10] b[11] b[12] vdd_hv_adc1 vss_hv_adc1 d[15] e[8] b[13] e[9] b[15] e[10] b[14] e[11] c[0] e[12] e[0] bctrl vdd_lv_regcor vss_lv_regcor vdd_hv_reg a[15] a[14] c[6] g[1] d[2] f[3] b[6] f[2] a[13] f[1] a[9] f[0] vss_lv_cor2 vdd_lv_cor2 c[8] d[4] d[3] vss_hv_io3 vdd_hv_io3 d[0] c[15] c[9] a[12] e[15] a[11] e[14] a[10] e[13] b[3] f[14] b[2] f[15] f[13] c[10] b[1] b[0] lqfp144 note : availability of port pin alternate functions depends on product selection. package pinouts and signal descriptions spc560p44lx, spc560p50lx 30/112 doc id 14723 rev 9 figure 3. 100-pin lqfp pinout ? airbag configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 nmi a[6] d[1] a[7] c[4] a[8] c[5] a[5] c[7] c[3] vss_lv_cor0 vdd_lv_cor0 vdd_hv_io1 vss_hv_io1 d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_cor3 vdd_lv_cor3 a[4] vpp_test d[14] c[14] c[13] d[12] vdd_hv_fl vss_hv_fl d[13] vss_lv_cor1 vdd_lv_cor1 a[3] vdd_hv_io2 vss_hv_io2 tdo tck tms tdi a[2] c[12] c[11] d[11] d[10] a[1] a[0] d[7] e[1] c[1] b[7] c[2] b[8] e[2] vdd_hv_adc0 vss_hv_adc0 b[9] b[10] b[11] b[12] vdd_hv_adc1 vss_hv_adc1 d[15] b[13] b[15] b[14] c[0] e[0] bctrl vdd_lv_regcor vss_lv_regcor vdd_hv_reg a[15] a[14] c[6] d[2] b[6] a[13] a[9] vss_lv_cor2 vdd_lv_cor2 c[8] d[4] d[3] vss_hv_io3 vdd_hv_io3 d[0] c[15] c[9] a[12] a[11] a[10] b[3] b[2] c[10] b[1] b[0] lqfp100 note : availability of port pin alternate functions depends on product selection. spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 31/112 figure 4. 100-pin lqfp pinout ? full featured configuration (top view) 2.2 pin description the following sections provide signal descriptions and related information about the functionality and configuration of the spc560p44lx, spc560p50lx devices. 2.2.1 power supply and reference voltage pins ta ble 5 lists the power supply and reference voltage for the spc560p44lx, spc560p50lx devices. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 nmi a[6] d[1] a[7] c[4] a[8] c[5] a[5] c[7] c[3] vss_lv_cor0 vdd_lv_cor0 vdd_hv_io1 vss_hv_io1 d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_cor3 vdd_lv_cor3 a[4] vpp_test d[14] c[14] c[13] d[12] vdd_hv_fl vss_hv_fl d[13] vss_lv_cor1 vdd_lv_cor1 a[3] vdd_hv_io2 vss_hv_io2 tdo tck tms tdi a[2] c[12] c[11] d[11] d[10] a[1] a[0] d[7] e[1] c[1] b[7] c[2] b[8] e[2] vdd_hv_adc0 vss_hv_adc0 b[9] b[10] b[11] b[12] vdd_hv_adc1 vss_hv_adc1 d[15] b[13] b[15] b[14] c[0] e[0] bctrl vdd_lv_regcor vss_lv_regcor vdd_hv_reg a[15] a[14] c[6] d[2] b[6] a[13] a[9] vss_lv_cor2 vdd_lv_cor2 c[8] d[4] d[3] vss_hv_io3 vdd_hv_io3 d[0] c[15] c[9] a[12] a[11] a[10] b[3] b[2] c[10] b[1] b[0] lqfp100 note : availability of port pin alternate functions depends on product selection. package pinouts and signal descriptions spc560p44lx, spc560p50lx 32/112 doc id 14723 rev 9 table 5. supply pins supply pin symbol description 100-pin 144-pin vreg control and power supply pins. pins available on 100-pin and 144-pin package. bctrl voltage regulator external npn ballast base control pin 47 69 v dd_hv_reg (3.3 v or 5.0 v) voltage regulator supply voltage 50 72 v dd_lv_regcor 1.2 v decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v ss_lv_regcor . 48 70 v ss_lv_regcor 1.2 v decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v dd_lv_regcor . 49 71 adc_0/adc_1 reference and supply voltage. pins available on 100-pin and 144-pin package. v dd_hv_adc0 (1) adc_0 supply and high reference voltage 33 50 v ss_hv_adc0 adc_0 ground and low reference voltage 34 51 v dd_hv_adc1 adc_1 supply and high reference voltage 39 56 v ss_hv_adc1 adc_1 ground and low reference voltage 40 57 power supply pins (3.3 v or 5.0 v). all pins available on 144-pin package. five pairs (v dd ; v ss ) available on 100-pin package. v dd_hv_io0 (2) input/output supply voltage ? 6 v ss_hv_io0 (2) input/output ground ? 7 v dd_hv_io1 input/output supply voltage 13 21 v ss_hv_io1 input/output ground 14 22 v dd_hv_io2 input/output supply voltage 63 91 v ss_hv_io2 input/output ground 62 90 v dd_hv_io3 input/output supply voltage 87 126 v ss_hv_io3 input/output ground 88 127 v dd_hv_fl code and data flash supply voltage 69 97 v ss_hv_fl code and data flash supply ground 68 96 v dd_hv_osc crystal oscillator amplifier supply voltage 16 27 v ss_hv_osc crystal oscillator amplifier ground 17 28 power supply pins (1.2 v). all pins available on 100-pin and 144-pin package. v dd_lv_cor0 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 12 18 v ss_lv_cor0 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 11 17 spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 33/112 2.2.2 system pins ta ble 5 and table 6 contain information on pin functions for the spc560p44lx, spc560p50lx devices. the pins listed in table 6 are single-function pins. the pins shown in ta ble 7 are multi-function pins, programmable via their respective pad configuration register (pcr) values. v dd_lv_cor1 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 65 93 v ss_lv_cor1 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 66 94 v dd_lv_cor2 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 92 131 v ss_lv_cor2 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 93 132 v dd_lv_cor3 1.2 v decoupling pins for on-chip pll modules. decoupling capacitor must be connected between this pin and v ss_lv_cor3 . 25 36 v ss_lv_cor3 1.2 v decoupling pins for on-chip pll modules. decoupling capacitor must be connected between this pin and v dd_lv_cor3 . 24 35 1. analog supply/ground and high/low reference lines are internally physically separat e, but are shorted via a double-bonding connection on v dd_hv_adcx /v ss_hv_adcx pins. 2. not available on 100-pin package. table 5. supply pins (continued) supply pin symbol description 100-pin 144-pin table 6. system pins symbol description direction pad speed (1) pin src = 0 src = 1 100-pin 144-pin dedicated pins. available on 100-pin and 144-pin package. mdo[0] nexus message data output?line 0 output only fast ? 9 nmi non-maskable interrupt input only slow ? 1 1 xtal analog output of the oscillator amplifier circuit; needs to be grounded if oscillator is used in bypass mode ???1829 extal ? analog input of oscillator amplifier circuit, when oscillator not in bypass mode ? analog input for clock generator when oscillator in bypass mode ???1930 package pinouts and signal descriptions spc560p44lx, spc560p50lx 34/112 doc id 14723 rev 9 2.2.3 pin muxing ta ble 7 defines the pin list and muxing for the spc560p44lx, spc560p50lx devices. each row of ta ble 7 shows all the possible ways of configuring each pin, via alternate functions. the default function assigned to each pin after reset is the alt0 function. spc560p44lx, spc560p50lx devices provide four main i/o pad types, depending on the associated functions: slow pads are the most common, providing a compromise between transition time and low electromagnetic emission. medium pads provide fast enough transition for serial communication channels with controlled current to reduce electromagnetic emission. fast pads provide maximum speed. they are used for improved nexus debugging capability. symmetric pads are designed to meet flexray requirements. medium and fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing ac performance. for more information, see the datasheet?s ?pad ac specifications? section. tms jtag state machine control bidirectional slow fast 59 87 tck jtag clock input only slow ? 60 88 tdi test data in input only slow medium 58 86 tdo test data out output only slow fast 61 89 reset pin, available on 100-pin and 144-pin package. reset bidirectional reset with schmitt trigger characteristics and noise filter bidirectional medium ? 20 31 test pin, available on 100-pin and 144-pin package. vpp_test pin for testing purpose only. to be tied to ground in normal operating mode. ???74107 1. scr values refer to the value assigned to the slew rate control bits of the pad configuration register. table 6. system pins (continued) symbol description direction pad speed (1) pin src = 0 src = 1 100-pin 144-pin spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 35/112 table 7. pin muxing port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin port a (16-bit) a[0] pcr[0] alt0 alt1 alt2 alt3 ? gpio[0] etc[0] sck f[0] eirq[0] siul etimer_0 dspi_2 fcu_0 siul i/o i/o o o i slow medium 51 73 a[1] pcr[1] alt0 alt1 alt2 alt3 ? gpio[1] etc[1] sout f[1] eirq[1] siul etimer_0 dspi_2 fcu_0 siul i/o i/o o o i slow medium 52 74 a[2] (6) pcr[2] alt0 alt1 alt2 alt3 ? ? ? gpio[2] etc[2] ? a[3] sin abs[0] eirq[2] siul etimer_0 ? flexpwm_0 dspi_2 mc_rgm siul i/o i/o ? o i i i slow medium 57 84 a[3] (6) pcr[3] alt0 alt1 alt2 alt3 ? ? gpio[3] etc[3] cs0 b[3] abs[2] eirq[3] siul etimer_0 dspi_2 flexpwm_0 mc_rgm siul i/o i/o i/o o i i slow medium 64 92 a[4] (6) pcr[4] alt0 alt1 alt2 alt3 ? ? gpio[4] etc[0] cs1 etc[4] fab eirq[4] siul etimer_1 dspi_2 etimer_0 mc_rgm siul i/o i/o o i/o i i slow medium 75 108 a[5] pcr[5] alt0 alt1 alt2 alt3 ? gpio[5] cs0 etc[5] cs7 eirq[5] siul dspi_1 etimer_1 dspi_0 siul i/o i/o i/o o i slow medium 8 14 a[6] pcr[6] alt0 alt1 alt2 alt3 ? gpio[6] sck ? ? eirq[6] siul dspi_1 ? ? siul i/o i/o ? ? i slow medium 2 2 package pinouts and signal descriptions spc560p44lx, spc560p50lx 36/112 doc id 14723 rev 9 a[7] pcr[7] alt0 alt1 alt2 alt3 ? gpio[7] sout ? ? eirq[7] siul dspi_1 ? ? siul i/o o ? ? i slow medium 4 10 a[8] pcr[8] alt0 alt1 alt2 alt3 ? ? gpio[8] ? ? ? sin eirq[8] siul ? ? ? dspi_1 siul i/o ? ? ? i i slow medium 6 12 a[9] pcr[9] alt0 alt1 alt2 alt3 ? gpio[9] cs1 ? b[3] fault[0] siul dspi_2 ? flexpwm_0 flexpwm_0 i/o o ? o i slow medium 94 134 a[10] pcr[10] alt0 alt1 alt2 alt3 ? gpio[10] cs0 b[0] x[2] eirq[9] siul dspi_2 flexpwm_0 flexpwm_0 siul i/o i/o o i/o i slow medium 81 118 a[11] pcr[11] alt0 alt1 alt2 alt3 ? gpio[11] sck a[0] a[2] eirq[10] siul dspi_2 flexpwm_0 flexpwm_0 siul i/o i/o o o i slow medium 82 120 a[12] pcr[12] alt0 alt1 alt2 alt3 ? gpio[12] sout a[2] b[2] eirq[11] siul dspi_2 flexpwm_0 flexpwm_0 siul i/o o o o i slow medium 83 122 a[13] pcr[13] alt0 alt1 alt2 alt3 ? ? ? gpio[13] ? b[2] ? sin fault[0] eirq[12] siul ? flexpwm_0 ? dspi_2 flexpwm_0 siul i/o ? o ? i i i slow medium 95 136 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 37/112 a[14] pcr[14] alt0 alt1 alt2 alt3 ? gpio[14] txd etc[4] ? eirq[13] siul safety port_0 etimer_1 ? siul i/o o i/o ? i slow medium 99 143 a[15] pcr[15] alt0 alt1 alt2 alt3 ? ? gpio[15] ? etc[5] ? rxd eirq[14] siul ? etimer_1 ? safety port_0 siul i/o ? i/o ? i i slow medium 100 144 port b (16-bit) b[0] pcr[16] alt0 alt1 alt2 alt3 ? gpio[16] txd etc[2] debug[0] eirq[15] siul flexcan_0 etimer_1 sscm siul i/o o i/o ? i slow medium 76 109 b[1] pcr[17] alt0 alt1 alt2 alt3 ? ? gpio[17] ? etc[3] debug[1] rxd eirq[16] siul ? etimer_1 sscm flexcan_0 siul i/o ? i/o ? i i slow medium 77 110 b[2] pcr[18] alt0 alt1 alt2 alt3 ? gpio[18] txd ? debug[2] eirq[17] siul lin_0 ? sscm siul i/o o ? ? i slow medium 79 114 b[3] pcr[19] alt0 alt1 alt2 alt3 ? gpio[19] ? ? debug[3] rxd siul ? ? sscm lin_0 i/o ? ? ? i slow medium 80 116 b[6] pcr[22] alt0 alt1 alt2 alt3 ? gpio[22] clkout cs2 ? eirq[18] siul mc_cgl dspi_2 ? siul i/o o o ? i slow medium 96 138 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin package pinouts and signal descriptions spc560p44lx, spc560p50lx 38/112 doc id 14723 rev 9 b[7] pcr[23] alt0 alt1 alt2 alt3 ? ? gpio[23] ? ? ? an[0] rxd siul ? ? ? adc_0 lin_0 input only ? ? 29 43 b[8] pcr[24] alt0 alt1 alt2 alt3 ? ? gpio[24] ? ? ? an[1] etc[5] siul ? ? ? adc_0 etimer_0 input only ? ? 31 47 b[9] pcr[25] alt0 alt1 alt2 alt3 ? gpio[25] ? ? ? an[11] siul ? ? ? adc_0 / adc_1 input only ? ? 35 52 b[10] pcr[26] alt0 alt1 alt2 alt3 ? gpio[26] ? ? ? an[12] siul ? ? ? adc_0 / adc_1 input only ? ? 36 53 b[11] pcr[27] alt0 alt1 alt2 alt3 ? gpio[27] ? ? ? an[13] siul ? ? ? adc_0 / adc_1 input only ? ? 37 54 b[12] pcr[28] alt0 alt1 alt2 alt3 ? gpio[28] ? ? ? an[14] siul ? ? ? adc_0 / adc_1 input only ? ? 38 55 b[13] pcr[29] alt0 alt1 alt2 alt3 ? ? gpio[29] ? ? ? an[0] rxd siul ? ? ? adc_1 lin_1 input only ? ? 42 60 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 39/112 b[14] pcr[30] alt0 alt1 alt2 alt3 ? ? ? gpio[30] ? ? ? an[1] etc[4] eirq[19] siul ? ? ? adc_1 etimer_0 siul input only ? ? 44 64 b[15] pcr[31] alt0 alt1 alt2 alt3 ? ? gpio[31] ? ? ? an[2] eirq[20] siul ? ? ? adc_1 siul input only ? ? 43 62 port c (16-bit) c[0] pcr[32] alt0 alt1 alt2 alt3 ? gpio[32] ? ? ? an[3] siul ? ? ? adc_1 input only ? ? 45 66 c[1] pcr[33] alt0 alt1 alt2 alt3 ? gpio[33] ? ? ? an[2] siul ? ? ? adc_0 input only ? ? 28 41 c[2] pcr[34] alt0 alt1 alt2 alt3 ? gpio[34] ? ? ? an[3] siul ? ? ? adc_0 input only ? ? 30 45 c[3] pcr[35] alt0 alt1 alt2 alt3 ? gpio[35] cs1 etc[4] txd eirq[21] siul dspi_0 etimer_1 lin_1 siul i/o o i/o o i slow medium 10 16 c[4] pcr[36] alt0 alt1 alt2 alt3 ? gpio[36] cs0 x[1] debug[4] eirq[22] siul dspi_0 flexpwm_0 sscm siul i/o i/o i/o ? i slow medium 5 11 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin package pinouts and signal descriptions spc560p44lx, spc560p50lx 40/112 doc id 14723 rev 9 c[5] pcr[37] alt0 alt1 alt2 alt3 ? ? gpio[37] sck ? debug[5] fault[3] eirq[23] siul dspi_0 ? sscm flexpwm_0 siul i/o i/o ? ? i i slow medium 7 13 c[6] pcr[38] alt0 alt1 alt2 alt3 ? gpio[38] sout b[1] debug[6] eirq[24] siul dspi_0 flexpwm_0 sscm siul i/o i/o o ? i slow medium 98 142 c[7] pcr[39] alt0 alt1 alt2 alt3 ? gpio[39] ? a[1] debug[7] sin siul ? flexpwm_0 sscm dspi_0 i/o ? o ? i slow medium 9 15 c[8] pcr[40] alt0 alt1 alt2 alt3 ? gpio[40] cs1 ? cs6 fault[2] siul dspi_1 ? dspi_0 flexpwm_0 i/o o ? o i slow medium 91 130 c[9] pcr[41] alt0 alt1 alt2 alt3 ? gpio[41] cs3 ? x[3] fault[2] siul dspi_2 ? flexpwm_0 flexpwm_0 i/o o ? i/o i slow medium 84 123 c[10] pcr[42] alt0 alt1 alt2 alt3 ? gpio[42] cs2 ? a[3] fault[1] siul dspi_2 ? flexpwm_0 flexpwm_0 i/o o ? o i slow medium 78 111 c[11] pcr[43] alt0 alt1 alt2 alt3 gpio[43] etc[4] cs2 cs0 siul etimer_0 dspi_2 dspi_3 i/o i/o o i/o slow medium 55 80 c[12] pcr[44] alt0 alt1 alt2 alt3 gpio[44] etc[5] cs3 cs1 siul etimer_0 dspi_2 dspi_3 i/o i/o o o slow medium 56 82 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 41/112 c[13] pcr[45] alt0 alt1 alt2 alt3 ? ? gpio[45] etc[1] ? ? ext_in ext_sync siul etimer_1 ? ? ctu_0 flexpwm_0 i/o i/o ? ? i i slow medium 71 101 c[14] pcr[46] alt0 alt1 alt2 alt3 gpio[46] etc[2] ext_tgr ? siul etimer_1 ctu_0 ? i/o i/o o ? slow medium 72 103 c[15] pcr[47] alt0 alt1 alt2 alt3 ? ? gpio[47] ca_tr_en etc[0] a[1] ext_in ext_sync siul flexray_0 etimer_1 flexpwm_0 ctu_0 flexpwm_0 i/o o i/o o i i slow symmetric 85 124 port d (16-bit) d[0] pcr[48] alt0 alt1 alt2 alt3 gpio[48] ca_tx etc[1] b[1] siul flexray_0 etimer_1 flexpwm_0 i/o o i/o o slow symmetric 86 125 d[1] pcr[49] alt0 alt1 alt2 alt3 ? gpio[49] ? etc[2] ext_trg ca_rx siul ? etimer_1 ctu_0 flexray_0 i/o ? i/o o i slow medium 3 3 d[2] pcr[50] alt0 alt1 alt2 alt3 ? gpio[50] ? etc[3] x[3] cb_rx siul ? etimer_1 flexpwm_0 flexray_0 i/o ? i/o i/o i slow medium 97 140 d[3] pcr[51] alt0 alt1 alt2 alt3 gpio[51] cb_tx etc[4] a[3] siul flexray_0 etimer_1 flexpwm_0 i/o o i/o o slow symmetric 89 128 d[4] pcr[52] alt0 alt1 alt2 alt3 gpio[52] cb_tr_en etc[5] b[3] siul flexray_0 etimer_1 flexpwm_0 i/o o i/o o slow symmetric 90 129 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin package pinouts and signal descriptions spc560p44lx, spc560p50lx 42/112 doc id 14723 rev 9 d[5] pcr[53] alt0 alt1 alt2 alt3 gpio[53] cs3 f[0] sout siul dspi_0 fcu_0 dspi_3 i/o o o o slow medium 22 33 d[6] pcr[54] alt0 alt1 alt2 alt3 ? gpio[54] cs2 sck ? fault[1] siul dspi_0 dspi_3 ? flexpwm_0 i/o o i/o ? i slow medium 23 34 d[7] pcr[55] alt0 alt1 alt2 alt3 ? gpio[55] cs3 f[1] cs4 sin siul dspi_1 fcu_0 dspi_0 dspi_3 i/o o o o i slow medium 26 37 d[8] pcr[56] alt0 alt1 alt2 alt3 ? gpio[56] cs2 ? cs5 fault[3] siul dspi_1 ? dspi_0 flexpwm_0 i/o o ? o i slow medium 21 32 d[9] pcr[57] alt0 alt1 alt2 alt3 gpio[57] x[0] txd ? siul flexpwm_0 lin_1 ? i/o i/o o ? slow medium 15 26 d[10] pcr[58] alt0 alt1 alt2 alt3 gpio[58] a[0] cs0 ? siul flexpwm_0 dspi_3 ? i/o o i/o ? slow medium 53 76 d[11] pcr[59] alt0 alt1 alt2 alt3 gpio[59] b[0] cs1 sck siul flexpwm_0 dspi_3 dspi_3 i/o o o i/o slow medium 54 78 d[12] pcr[60] alt0 alt1 alt2 alt3 ? gpio[60] x[1] ? ? rxd siul flexpwm_0 ? ? lin_1 i/o i/o ? ? i slow medium 70 99 d[13] pcr[61] alt0 alt1 alt2 alt3 gpio[61] a[1] cs2 sout siul flexpwm_0 dspi_3 dspi_3 i/o o o o slow medium 67 95 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 43/112 d[14] pcr[62] alt0 alt1 alt2 alt3 ? gpio[62] b[1] cs3 ? sin siul flexpwm_0 dspi_3 ? dspi_3 i/o o o ? i slow medium 73 105 d[15] pcr[63] alt0 alt1 alt2 alt3 ? gpio[63] ? ? ? an[4] siul ? ? ? adc_1 input only ? ? 41 58 port e(16-bit) e[0] pcr[64] alt0 alt1 alt2 alt3 ? gpio[64] ? ? ? an[5] siul ? ? ? adc_1 input only ? ? 46 68 e[1] pcr[65] alt0 alt1 alt2 alt3 ? gpio[65] ? ? ? an[4] siul ? ? ? adc_0 input only ? ? 27 39 e[2] pcr[66] alt0 alt1 alt2 alt3 ? gpio[66] ? ? ? an[5] siul ? ? ? adc_0 input only ? ? 32 49 e[3] pcr[67] alt0 alt1 alt2 alt3 ? gpio[67] ? ? ? an[6] siul ? ? ? adc_0 input only ? ? ? 40 e[4] pcr[68] alt0 alt1 alt2 alt3 ? gpio[68] ? ? ? an[7] siul ? ? ? adc_0 input only ? ? ? 42 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin package pinouts and signal descriptions spc560p44lx, spc560p50lx 44/112 doc id 14723 rev 9 e[5] pcr[69] alt0 alt1 alt2 alt3 ? gpio[69] ? ? ? an[8] siul ? ? ? adc_0 input only ? ? ? 44 e[6] pcr[70] alt0 alt1 alt2 alt3 ? gpio[70] ? ? ? an[9] siul ? ? ? adc_0 input only ? ? ? 46 e[7] pcr[71] alt0 alt1 alt2 alt3 ? gpio[71] ? ? ? an[10] siul ? ? ? adc_0 input only ? ? ? 48 e[8] pcr[72] alt0 alt1 alt2 alt3 ? gpio[72] ? ? ? an[6] siul ? ? ? adc_1 input only ? ? ? 59 e[9] pcr[73] alt0 alt1 alt2 alt3 ? gpio[73] ? ? ? an[7] siul ? ? ? adc_1 input only ? ? ? 61 e[10] pcr[74] alt0 alt1 alt2 alt3 ? gpio[74] ? ? ? an[8] siul ? ? ? adc_1 input only ? ? ? 63 e[11] pcr[75] alt0 alt1 alt2 alt3 ? gpio[75] ? ? ? an[9] siul ? ? ? adc_1 input only ? ? ? 65 e[12] pcr[76] alt0 alt1 alt2 alt3 ? gpio[76] ? ? ? an[10] siul ? ? ? adc_1 input only ? ? ? 67 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 45/112 e[13] pcr[77] alt0 alt1 alt2 alt3 ? gpio[77] sck ? ? eirq[25] siul dspi_3 ? ? siul i/o i/o ? ? i slow medium ? 117 e[14] pcr[78] alt0 alt1 alt2 alt3 ? gpio[78] sout ? ? eirq[26] siul dspi_3 ? ? siul i/o o ? ? i slow medium ? 119 e[15] pcr[79] alt0 alt1 alt2 alt3 ? ? gpio[79] ? ? ? sin eirq[27] siul ? ? ? dspi_3 siul i/o ? ? ? i i slow medium ? 121 port f (16-bit) f[0] pcr[80] alt0 alt1 alt2 alt3 ? gpio[80] dbg0 cs3 ? eirq[28] siul flexray_0 dspi_3 ? siul i/o o o ? i slow medium ? 133 f[1] pcr[81] alt0 alt1 alt2 alt3 ? gpio[81] dbg1 cs2 ? eirq[29] siul flexray_0 dspi_3 ? siul i/o o o ? i slow medium ? 135 f[2] pcr[82] alt0 alt1 alt2 alt3 gpio[82] dbg2 cs1 ? siul flexray_0 dspi_3 ? i/o o o ? slow medium ? 137 f[3] pcr[83] alt0 alt1 alt2 alt3 gpio[83] dbg3 cs0 ? siul flexray_0 dspi_3 ? i/o o i/o ? slow medium ? 139 f[4] pcr[84] alt0 alt1 alt2 alt3 gpio[84] mdo[3] ? ? siul nexus_0 ? ? i/o o ? ? slow fast ? 4 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin package pinouts and signal descriptions spc560p44lx, spc560p50lx 46/112 doc id 14723 rev 9 f[5] pcr[85] alt0 alt1 alt2 alt3 gpio[85] mdo[2] ? ? siul nexus_0 ? ? i/o o ? ? slow fast ? 5 f[6] pcr[86] alt0 alt1 alt2 alt3 gpio[86] mdo[1] ? ? siul nexus_0 ? ? i/o o ? ? slow fast ? 8 f[7] pcr[87] alt0 alt1 alt2 alt3 gpio[87] mcko ? ? siul nexus_0 ? ? i/o o ? ? slow fast ? 19 f[8] pcr[88] alt0 alt1 alt2 alt3 gpio[88] mseo1 ? ? siul nexus_0 ? ? i/o o ? ? slow fast ? 20 f[9] pcr[89] alt0 alt1 alt2 alt3 gpio[89] mseo0 ? ? siul nexus_0 ? ? i/o o ? ? slow fast ? 23 f[10] pcr[90] alt0 alt1 alt2 alt3 gpio[90] evto ? ? siul nexus_0 ? ? i/o o ? ? slow fast ? 24 f[11] pcr[91] alt0 alt1 alt2 alt3 ? gpio[91] ? ? ? evti siul ? ? ? nexus_0 i/o ? ? ? i slow medium ? 25 f[12] pcr[92] alt0 alt1 alt2 alt3 gpio[92] etc[3] ? ? siul etimer_1 ? ? i/o i/o ? ? slow medium ? 106 f[13] pcr[93] alt0 alt1 alt2 alt3 gpio[92] etc[4] ? ? siul etimer_1 ? ? i/o i/o ? ? slow medium ? 112 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin spc560p44lx, spc560p50lx package pinouts and signal descriptions doc id 14723 rev 9 47/112 f[14] pcr[94] alt0 alt1 alt2 alt3 gpio[94] txd ? ? siul lin_1 ? ? i/o o ? ? slow medium ? 115 f[15] pcr[95] alt0 alt1 alt2 alt3 ? gpio[95] ? ? ? rxd siul ? ? ? lin_1 i/o ? ? ? i slow medium ? 113 port g (12-bit) g[0] pcr[96] alt0 alt1 alt2 alt3 ? gpio[96] f[0] ? ? eirq[30] siul fcu_0 ? ? siul i/o o ? ? i slow medium ? 38 g[1] pcr[97] alt0 alt1 alt2 alt3 ? gpio[97] f[1] ? ? eirq[31] siul fcu_0 ? ? siul i/o o ? ? i slow medium ? 141 g[2] pcr[98] alt0 alt1 alt2 alt3 gpio[98] x[2] ? ? siul flexpwm_0 ? ? i/o i/o ? ? slow medium ? 102 g[3] pcr[99] alt0 alt1 alt2 alt3 gpio[99] a[2] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium ? 104 g[4] pcr[100] alt0 alt1 alt2 alt3 gpio[100] b[2] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium ? 100 g[5] pcr[101] alt0 alt1 alt2 alt3 gpio[101] x[3] ? ? siul flexpwm_0 ? ? i/o i/o ? ? slow medium ? 85 g[6] pcr[102] alt0 alt1 alt2 alt3 gpio[102] a[3] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium ? 98 table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin package pinouts and signal descriptions spc560p44lx, spc560p50lx 48/112 doc id 14723 rev 9 g[7] pcr[103] alt0 alt1 alt2 alt3 gpio[103] b[3] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium ? 83 g[8] pcr[104] alt0 alt1 alt2 alt3 ? gpio[104] ? ? ? fault[0] siul ? ? ? flexpwm_0 i/o ? ? ? i slow medium ? 81 g[9] pcr[105] alt0 alt1 alt2 alt3 ? gpio[105] ? ? ? fault[1] siul ? ? ? flexpwm_0 i/o ? ? ? i slow medium ? 79 g[10] pcr[106] alt0 alt1 alt2 alt3 ? gpio[106] ? ? ? fault[2] siul ? ? ? flexpwm_0 i/o ? ? ? i slow medium ? 77 g[11] pcr[107] alt0 alt1 alt2 alt3 ? gpio[107] ? ? ? fault[3] siul ? ? ? flexpwm_0 i/o ? ? ? i slow medium ? 75 1. alt0 is the primary (default) function for each port after reset. 2. alternate functions are chosen by setting the values of the pcr[pa] bitfields inside the siu module. pcr[pa] = 00 alt0; pcr[pa] = 01 alt1; pcr[pa] = 10 alt2; pcr[pa] = 11 alt3. this is intended to select the output functions; to use one of the input-only functions, the p cr[ibe] bit must be written to ?1?, regardless of the values selected in the pcr[pa] bitfields. for this reason, the va lue corresponding to an input only function is reported as ???. 3. module included on the mcu. 4. multiple inputs are routed to all respective modules internally . the input of some modules must be configured by setting the values of the psmi[padsel x ] bitfields inside the siul module. 5. programmable via the src (slew rate control) bits in the respective pad configuration register. 6. weak pull down during reset. table 7. pin muxing (continued) port pin pad configuration register (pcr) alternate function (1), (2) functions peripheral (3) i/o direction (4) pad speed (5) pin no. src = 0 src = 1 100-pin 144-pin spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 49/112 3 electrical characteristics 3.1 introduction this section contains device electrical characteristics as well as temperature and power considerations. this microcontroller contains input protection against damage due to high static voltages. however, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this can be done by the internal pull-up or pull-down resistors, which are provided by the device for most general purpose pins. the following tables provide the device characteristics and its demands on the system. in the tables where the device logic provides signals with their respective timing characteristics, the symbol ?cc? for controller characteristics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requirement is included in the symbol column. caution: all of the following parameter values can vary depending on the application and must be confirmed during silicon characterization or silicon reliability trial. 3.2 parameter classification the electrical parameters are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 8 are used and the parameters are tagged accordingly in the tables where appropriate. note: the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 8. parameter classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. electrical characteristics spc560p44lx, spc560p50lx 50/112 doc id 14723 rev 9 3.3 absolute maximum ratings table 9. absolute maximum ratings (1) symbol parameter conditions value unit min max (2) v ss sr device ground ? 0 0 v v dd_hv_iox (3) sr 3.3 v / 5.0 v input/output supply voltage with respect to ground (v ss ) ??0.3 6.0v v ss_hv_iox sr input/output ground voltage with respect to ground (v ss ) ??0.1 0.1v v dd_hv_fl sr 3.3 v / 5.0 v code and data flash supply voltage with respect to ground (v ss ) ? ?0.3 6.0 v relative to v dd_hv_iox v dd_hv_iox + 0.3 v ss_hv_fl sr code and data flash ground with respect to ground (v ss ) ??0.1 0.1v v dd_hv_osc sr 3.3 v / 5.0 v crystal oscillator amplifier supply voltage with respect to ground (v ss ) ? ?0.3 6.0 v relative to v dd_hv_iox v dd_hv_iox + 0.3 v ss_hv_osc sr 3.3 v / 5.0 v crystal oscillator amplifier reference voltage with respect to ground (v ss ) ??0.1 0.1v v dd_hv_reg sr 3.3 v / 5.0 v voltage regulator supply voltage with respect to ground (v ss ) ? ?0.3 6.0 v relative to v dd_hv_iox v dd_hv_iox + 0.3 v dd_hv_adc0 (4) sr 3.3 v / 5.0 v adc_0 supply and high reference voltage with respect to ground (v ss ) v dd_hv_reg < 2.7 v ?0.3 v dd_hv_reg + 0.3 v v dd_hv_reg > 2.7 v 6.0 v ss_hv_adc0 sr adc_0 ground and low reference voltage with respect to ground (v ss ) ??0.1 0.1v v dd_hv_adc1 ( 4) sr 3.3 v / 5.0 v adc_0 supply and high reference voltage with respect to ground (v ss ) v dd_hv_reg < 2.7 v ?0.3 v dd_hv_reg + 0.3 v v dd_hv_reg > 2.7 v 6.0 v ss_hv_adc1 sr adc_1 ground and low reference voltage with respect to ground (v ss ) ??0.1 0.1v tv dd sr slope characteristics on all v dd during power up (5) with respect to ground (v ss ) ?3.0 500 x 10 3 (0.5 [v/s]) v/s v in sr voltage on any pin with respect to ground (v ss_hv_iox ) with respect to ground (v ss ) ? ?0.3 6.0 v relative to v dd_hv_iox v dd_hv_iox +0.3 spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 51/112 figure 5 shows the constraints of the different power supplies. v inan0 sr adc0 and shared adc0/1 analog input voltage (6) v dd_hv_reg > 2.7 v v ss_hv_adv0 ? 0.3 v dd_hv_adv0 + 0.3 v v dd_hv_reg < 2.7 v v ss_hv_adv0 v dd_hv_adv0 v v inan1 sr adc1 analog input voltage (7) v dd_hv_reg > 2.7 v v ss_hv_adv1 ? 0.3 v dd_hv_adv1 + 0.3 v v dd_hv_reg < 2.7 v v ss_hv_adv1 v dd_hv_adv1 v i injpad sr injected input current on any pin during overload condition ??10 10ma i injsum sr absolute sum of all injected input currents during overload condition ??50 50 ma i vdd_lv sr low voltage static current sink through v dd_lv ?? 155ma t stg sr storage temperature ? ?55 150 c t j sr junction temperature under bias ? ?40 150 c 1. functional operating conditions are given in the dc electrical characteristics. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. absolute maximum voltages are currently maximum burn-in voltages. absolute maximum specifications for device stress have not yet been determined. 3. the difference between each couple of voltage supplies must be less than 300 mv, |v dd_hv_ioy ? v dd_hv_iox | < 300 mv. 4. the difference between adc voltage supplies must be less than 100 mv, |v dd_hv_adc1 ? v dd_hv_adc0 | < 100 mv. 5. guaranteed by device validation 6. not allowed to refer this voltage to v dd_hv_adv1 , v ss_hv_adv1 7. not allowed to refer this voltage to v dd_hv_adv0 , v ss_hv_adv0 table 9. absolute maximum ratings (1) (continued) symbol parameter conditions value unit min max (2) electrical characteristics spc560p44lx, spc560p50lx 52/112 doc id 14723 rev 9 figure 5. power supplies constraints (?0.3 v v dd_hv_iox 6.0 v) the spc560p44lx, spc560p50lx supply architecture allows of having adc supply managed independently from standard v dd_hv supply. figure 6 shows the constraints of the adc power supply. figure 6. independent adc supply (?0.3 v v dd_hv_reg 6.0 v) vdd_hv_xxx vdd_hv_iox ?0.3 v 6.0 v ?0.3 v 6.0 v vdd_hv_adcx 6.0 v vdd_hv_reg ?0.3 v 2.7 v ?0.3 v 6.0 v spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 53/112 3.4 recommended operating conditions table 10. recommended operating conditions (5.0 v) symbol parameter conditions value unit min max (1) v ss sr device ground ? 0 0 v v dd_hv_iox (2) sr 5.0 v input/output supply voltage ?4.5 5.5v v ss_hv_iox sr input/output ground voltage ? 0 0 v v dd_hv_fl sr 5.0 v code and data flash supply voltage ?4.5 5.5 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v ss_hv_fl sr code and data flash ground ? 0 0 v v dd_hv_osc sr 5.0 v crystal oscillator amplifier supply voltage ?4.5 5.5 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v ss_hv_osc sr 5.0 v crystal oscillator amplifier reference voltage ?0 0v v dd_hv_reg sr 5.0 v voltage regulator supply voltage ?4.5 5.5 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v dd_hv_adc0 (3) sr 5.0 v adc_0 supply and high reference voltage ?4.5 5.5 v relative to v dd_hv_reg v dd_hv_reg ? 0.1 ? v ss_hv_adc0 sr adc_0 ground and low reference voltage ?0 0v v dd_hv_adc1 (3) sr 5.0 v adc_1 supply and high reference voltage ?4.5 5.5 v relative to v dd_hv_reg v dd_hv_reg ? 0.1 ? v ss_hv_adc1 sr adc_1 ground and low reference voltage ?0 0v v dd_lv_regcor (4), (5) cc internal supply voltage ? ? ? v v ss_lv_regcor (4) sr internal reference voltage ? 0 0 v v dd_lv_corx (4),(5) cc internal supply voltage ? ? ? v v ss_lv_corx (4) sr internal reference voltage ? 0 0 v t a sr ambient temperature under bias f cpu = 64 mhz ?40 105 c f cpu = 60 mhz ?40 125 1. parametric figures can be out of specification when voltage drops below 4.5 v, however, guarant eeing the full functionality. in particular, adc electrical characteristics and i/ os dc electrical specification may not be guaranteed. 2. the difference between each couple of voltage supplies must be less than 100 mv, |v dd_hv_ioy ? v dd_hv_iox | < 100 mv. electrical characteristics spc560p44lx, spc560p50lx 54/112 doc id 14723 rev 9 3. the difference between adc voltage supplies must be less than 100 mv, |v dd_hv_adc1 ? v dd_hv_adc0 | < 100 mv. 4. to be connected to emitter of external npn. low voltage supplies are not under user cont rol?they are produced by an on- chip voltage regulator?but for the device to function properly the low voltage grounds (v ss_lv_xxx ) must be shorted to high voltage grounds (v ss_hv_xxx ) and the low voltage supply pins (v dd_lv_xxx ) must be connected to the external ballast emitter. 5. the low voltage supplies (v dd_lv_xxx ) are not all independent. v dd_lv_cor1 and v dd_lv_cor2 are shorted internally via double bonding connections with lines that provide the low voltage supply to the data flash module. similarly, v ss_lv_cor1 and v ss_lv_cor2 are internally shorted. v dd_lv_regcor and v dd_lv_regcorx are physically shorted internally, as are v ss_lv_regcor and v ss_lv_corx . table 11. recommended operating conditions (3.3 v) symbol parameter conditions value unit min max (1) v ss sr device ground ? 0 0 v v dd_hv_iox (2) sr 3.3 v input/output supply voltage ?3.0 3.6v v ss_hv_iox sr input/output ground voltage ? 0 0 v v dd_hv_fl sr 3.3 v code and data flash supply voltage ?3.0 3.6 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v ss_hv_fl sr code and data flash ground ? 0 0 v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage ?3.0 3.6 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ?0 0v v dd_hv_reg sr 3.3 v voltage regulator supply voltage ?3.0 3.6 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v dd_hv_adc0 (3) sr 3.3 v adc_0 supply and high reference voltage ?3.0 5.5 v relative to v dd_hv_reg v dd_hv_reg ? 0.1 5.5 v ss_hv_adc0 sr adc_0 ground and low reference voltage ?0 0v v dd_hv_adc1 (3) sr 3.3 v adc_1 supply and high reference voltage ?3.0 5.5 v relative to v dd_hv_reg v dd_hv_reg ? 0.1 5.5 v ss_hv_adc1 sr adc_1 ground and low reference voltage ?0 0v v dd_lv_regcor (4), (5) cc internal supply voltage ? ? ? v v ss_lv_regcor (4) sr internal reference voltage ? 0 0 v v dd_lv_corx (4),(5) cc internal supply voltage ? ? ? v spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 55/112 figure 7 shows the constraints of the different power supplies. figure 7. power supplies constraints (3.0 v v dd_hv_iox 5.5 v) v ss_lv_corx (4) sr internal reference voltage ? 0 0 v t a sr ambient temperature under bias f cpu = 64 mhz ?40 105 c f cpu = 60 mhz ?40 125 1. parametric figures can be out of specification when voltage drops below 4.5 v, however, guarant eeing the full functionality. in particular, adc electrical characteristics and i/ os dc electrical specification may not be guaranteed. 2. the difference between each couple of voltage supplies must be less than 100 mv, |v dd_hv_ioy ? v dd_hv_iox | < 100 mv. 3. the difference between each couple of voltage supplies must be less than 100 mv, |v dd_hv_adc1 ? v dd_hv_adc0 | < 100 mv. as long as that condition is met, adc_0 and adc_1 can be operated at 5 v with the rest of the device operating at 3.3 v. 4. to be connected to emitter of external npn. low voltage supplies are not under user cont rol?they are produced by an on- chip voltage regulator?but for the device to function properly the low voltage grounds (v ss_lv_xxx ) must be shorted to high voltage grounds (v ss_hv_xxx ) and the low voltage supply pins (v dd_lv_xxx ) must be connected to the external ballast emitter. 5. the low voltage supplies (v dd_lv_xxx ) are not all independent. v dd_lv_cor1 and v dd_lv_cor2 are shorted internally via double bonding connections with lines that provide the low voltage supply to the data flash module. similarly, v ss_lv_cor1 and v ss_lv_cor2 are internally shorted. v dd_lv_regcor and v dd_lv_regcorx are physically shorted internally, as are v ss_lv_regcor and v ss_lv_corx . table 11. recommended operating c onditions (3.3 v) (continued) symbol parameter conditions value unit min max (1) vdd_hv_xxx vdd_hv_iox 3.0 v 5.5 v 3.0 v 5.5 v 3.3 v 3.3 v note : io ac and dc characteristics are guaranteed only in the range of 3.0?3.6 v when pad3v5v is low, and in the range of 4.5?5.5 v when pad3v5v is high. electrical characteristics spc560p44lx, spc560p50lx 56/112 doc id 14723 rev 9 the spc560p44lx, spc560p50lx supply architecture allows the adc supply to be managed independently from the standard v dd_hv supply. figure 8 shows the constraints of the adc power supply. figure 8. independent adc supply (3.0 v v dd_hv_reg 5.5 v) 3.5 thermal characteristics 3.5.1 package thermal characteristics 5.5 v 3.0 v vdd_hv_reg 3.0 v 5.5 v vdd_hv_adcx table 12. thermal characteristics for 144-pin lqfp symbol parameter conditions typical value unit r ja thermal resistance junction-to-ambient, natural convection (1) 1. junction-to-ambient thermal resistance determi ned per jedec jesd51-7. thermal test board meets jedec specification for this package. single layer board?1s 54.2 c/ w four layer board? 2s2p 44.4 c/ w r jb thermal resistance junction-to-board (2) four layer board? 2s2p 29.9 c/ w r jctop thermal resistance junction-to-case (top) (3) single layer board?1s 9.3 c/ w jb junction-to-board, natural convection (4) operating conditions 30.2 c/ w jc junction-to-case, natural convection (5) operating conditions 0.8 c/ w spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 57/112 3.5.2 general notes for specifications at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : equation 1 t j = t a + (r ja * p d ) where: t a = ambient temperature for the package (c) r ja = junction to ambient thermal resistance (c/w) p d = power dissipation in the package (w) the junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two values in 2. junction-to-board thermal resistance determined pe r jedec jesd51-8. thermal test board meets jedec specification for the specified package. 3. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. r eported value includes the thermal resistance of the interface layer. 4. thermal characterization parameter indicating the temperature difference between the board and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jb. 5. thermal characterization parameter indicating the temperature difference between the case and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jc. table 13. thermal characteristics for 100-pin lqfp symbol parameter conditions typical value unit r ja thermal resistance junction-to-ambient, natural convection (1) 1. junction-to-ambient thermal resistance determi ned per jedec jesd51-7. thermal test board meets jedec specification for this package. single layer board?1s 47.3 c/ w four layer board?2s2p 35.3 c/ w r jb thermal resistance junction-to-board (2) 2. junction-to-board thermal resistance determined pe r jedec jesd51-8. thermal test board meets jedec specification for the specified package. four layer board?2s2p 19.1 c/ w r jctop thermal resistance junction-to-case (top) (3) 3. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. r eported value includes the thermal resistance of the interface layer. single layer board?1s 9.7 c/ w jb junction-to-board, natural convection (4) 4. thermal characterization parameter indicating the temperature difference between the board and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jb. operating conditions 19.1 c/ w jc junction-to-case, natural convection (5) 5. thermal characterization parameter indicating the temperature difference between the case and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jc. operating conditions 0.8 c/ w electrical characteristics spc560p44lx, spc560p50lx 58/112 doc id 14723 rev 9 common usage: the value determined on a single layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed in equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: equation 2 r ja = r jc + r ca where: r ja = junction to ambient thermal resistance (c/w) r jc = junction to case thermal resistance (c/w) r ca = case to ambient thermal resistance (c/w) r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case to ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using equation 3 : equation 3 t j = t t + ( jt x p d ) where: t t = thermocouple temperature on top of the package (c) jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 u.s.a. (408) 943-6900 mil-spec and eia/jesd (jedec) specifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 59/112 1. c.e. triplett and b. joiner, an experimental characterization of a 272 pbga within an automotive engine controller module , proceedings of semitherm, san diego, 1998, pp. 47?54. 2. g. kromann, s. shidore, and s. addison, thermal modeling of a pbga for air-cooled applications , electronic packaging and production, pp. 53?58, march 1998. 3. b. joiner and v. adams, measurement and simulation of junction to board thermal resistance and its application in thermal modeling , proceedings of semitherm, san diego, 1999, pp. 212?220. 3.6 electromagnetic interference (emi) characteristics 3.7 electrostatic discharge (esd) characteristics 3.8 power management electrical characteristics 3.8.1 voltage regulator electrical characteristics the internal voltage regulator requires an external npn ballast to be connected as shown in figure 9 . table 16 contains all approved npn ballast components. capacitances should be placed on the board as near as possible to the associated pins. care should also be taken to limit the serial inductance of the v dd_hv_reg , bctrl and v dd_lv_corx pins to less than table 14. emi testing specifications symbol parameter conditions clocks frequency level (max) unit v eme radiated emissions device configuration, test conditions and em testing per standard iec61967-2 supply voltage = 5 v dc ambient temperature = 25 c worst-case orientation f osc 8mhz f cpu 64 mhz no pll frequency modulation 150 khz?150 mhz 16 dbv 150?1000 mhz 15 iec level m ? f osc 8mhz f cpu 64 mhz 1% pll frequency modulation 150 khz?150 mhz 15 dbv 150?1000 mhz 14 iec level m ? table 15. esd ratings (1),(2) symbol parameter conditions value unit v esd(hbm) s r electrostatic discharge (human body model) ? 2000 v v esd(cdm) s r electrostatic discharge (charged device model) ? 750 (corners) v 500 (other) 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the device no longer m eets the device specification requirements. complete dc parametric and functional test ing shall be performed per applic able device specification at room temperature followed by hot temperature, unless specified other wise in the device specification. electrical characteristics spc560p44lx, spc560p50lx 60/112 doc id 14723 rev 9 l reg , see table 17 . note: the voltage regulator output cannot be used to drive external circuits. output pins are used only for decoupling capacitances. v dd_lv_cor must be generated using internal regulator and external npn transistor. it is not possible to provide v dd_lv_cor through external regulator. for the spc560p44lx, spc560p50lx microcontroller, capacitors, with total values not below c dec1 , should be placed between v dd_lv_corx /v ss_lv_corx close to external ballast transistor emitter. 4 capacitors, with total values not below c dec2 , should be placed close to microcontroller pins between each v dd_lv_corx /v ss_lv_corx supply pairs and the v dd_lv_regcor /v ss_lv_regcor pair . additionally, capacitors with total values not below c dec3 , should be placed between the v dd_hv_reg /v ss_hv_reg pins close to ballast collector. capacitors values have to take into account capacitor accuracy, aging and variation versus temperature. all reported information are valid for voltage and temperature ranges described in recommended operating condition, tab le 10 and table 11 . figure 9. configuration with resistor on base table 16. approved npn ballast components (configuration with resistor on base) part manufacturer approved derivatives (1) bcp68 on semi bcp68 nxp bcp68-25 infineon bcp68-25 bcx68 infineon bcx68-10;bcx68-16;bcx68-25 bc868 nxp bc868 bctrl vdd_lv_cor c dec3 c dec2 c dec1 vdd_hv_reg bjt (1) spc560p44lx, 1. refer to table 16 . r b spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 61/112 bc817 infineon bc817-16;bc817-25;bc817su; nxp bc817-16;bc817-25 bcp56 st bcp56-16 infineon bcp56-10;bcp56-16 on semi bcp56-10 nxp bcp56-10;bcp56-16 1. for automotive applications please check with the appropriate transistor vendor for automotive grade certification table 16. approved npn ballast components (configuration with resistor on base) part manufacturer approved derivatives (1) table 17. voltage regulator electrical characte ristics (configuration with resistor on base) symbol c parameter conditions value unit min typ max v dd_lv_regcor cc p output voltage under maximum load run supply current configuration post-trimming 1.15 ? 1.32 v r b sr ? external resistance on bipolar junction transistor (bjt) base ?18?22k c dec1 sr ? external decoupling/stability ceramic capacitor bjt from table 16 . 3 capacitances (i.e. x7r or x8r capacitors) with nominal value of 10 f 19.5 30 ? f bjt bc817, one capacitance of 22 f 14.3 22 f r reg sr ? resulting esr of all three capacitors of c dec1 bjt from table 16 . 3x10 f. absolute maximum value between 100 khz and 10 mhz ??50m resulting esr of the unique capacitor c dec1 bjt bc817, 1x 22 f. absolute maximum value between 100 khz and 10 mhz 10 ? 40 m c dec2 sr ? external decoupling/stability ceramic capacitor 4 capacitances (i.e. x7r or x8r capacitors) with nominal value of 440 nf 1200 1760 ? nf c dec3 sr ? external decoupling/stability ceramic capacitor on v dd_hv_reg 3 capacitances (i.e. x7r or x8r capacitors) with nominal value of 10 f; c dec3 has to be equal or greater than c dec1 19.5 30 ? f l reg sr ? resulting esl of v dd_hv_reg , bctrl and v dd_lv_corx pins ???15nh electrical characteristics spc560p44lx, spc560p50lx 62/112 doc id 14723 rev 9 figure 10. configuration without resistor on base bctrl vdd_lv_cor c dec3 c dec2 c dec1 vdd_hv_reg spc560p44lx, bcp56, bcp68, bcx68, bc817 table 18. voltage regulator electrical characte ristics (configuration without resistor on base) symbol c parameter conditions value unit min typ max v dd_lv_regcor cc p output voltage under maximum load run supply current configuration post-trimming 1.15 ? 1.32 v c dec1 sr ? external decoupling/stability ceramic capacitor 4 capacitances 40 56 ? f r reg sr ? resulting esr of all four c dec1 absolute maximum value between 100 khz and 10 mhz ??45m c dec2 sr ? external decoupling/stability ceramic capacitor 4 capacitances of 100 nf each 400 ? ? nf c dec3 sr ? external decoupling/stability ceramic capacitor on vdd_hv_reg ?40??f l reg sr ? resulting esl of v dd_hv_reg , bctrl and v dd_lv_corx pins ???15nh spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 63/112 3.8.2 voltage monitor electrical characteristics the device implements a power-on reset module to ensure correct power-up initialization, as well as three low voltage detectors to monitor the v dd and the v dd_lv voltage while device is supplied: por monitors v dd during the power-up phase to ensure device is maintained in a safe reset state lvdhv3 monitors v dd to ensure device reset below minimum functional supply lvdhv5 monitors v dd when application uses device in the 5.0 v 10 % range lvdlvcor monitors low voltage digital power domain 3.9 power up/down sequencing to prevent an overstress event or a malfunction within and outside the device, the spc560p44lx, spc560p50lx implements the following sequence to ensure each module is started only when all conditions for switching it on are available: a power_on module working on voltage regulator supply controls the correct start- up of the regulator. this is a key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5v. associated power_on (or por) signal is active low. several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage regulator, i/os, flash memory and low voltage domain). lvds are gated low when power_on is active. a power_ok signal is generated when all critical supplies monitored by the lvd are available. this signal is active high and released to all modules including i/os, flash table 19. low voltage monitor electrical characteristics symbol c parameter conditions (1) value unit min max v porh t power-on reset threshold ? 1.5 2.7 v v porup p supply for functional por module t a = 25 c 1.0 ? v v reglvdmok_h p regulator low voltage detector high threshold ? ? 2.95 v v reglvdmok_l p regulator low voltage detector low threshold ? 2.6 ? v v fllvdmok_h p flash low voltage detector high threshold ? ? 2.95 v v fllvdmok_l p flash low voltage detector low threshold ? 2.6 ? v v iolvdmok_h p i/o low voltage detector high threshold ? ? 2.95 v v iolvdmok_l p i/o low voltage detector low threshold ? 2.6 ? v v iolvdm5ok_h p i/o 5v low voltage detector high threshold ? ? 4.4 v v iolvdm5ok_l p i/o 5v low voltage detector low threshold ? 3.8 ? v v mlvddok_h p digital supply low voltage detector high ? ? 1.145 v v mlvddok_l p digital supply low voltage detector low ? 1.08 ? v 1. v dd = 3.3v 10% / 5.0v 10%, t a = ?40 c to t a max , unless otherwise specified electrical characteristics spc560p44lx, spc560p50lx 64/112 doc id 14723 rev 9 memory and rc16 oscillator needed during power-up phase and reset phase. when power_ok is low the associated module are set into a safe state. figure 11. power-up typical sequence figure 12. power-down typical sequence vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 0v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 p1 0v 1.2v internal reset generation module fsm ~1us v por_up v porh v lvdhv3h v mlvdok_h vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 idle 0v 1.2v internal reset generation module fsm v lvdhv3l v porh 0v spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 65/112 figure 13. brown-out typical sequence 3.10 dc electrical characteristics 3.10.1 nvusro register portions of the device configuration, such as high voltage supply, and watchdog enable/disable after reset are controlled via bit values in the non-volatile user options (nvusro) register. for a detailed description of the nvusro register, please refer to the device reference manual. nvusro[pad3v5v] field description the dc electrical characteristics are dependent on the pad3v5v bit value. tab le 20 shows how nvusro[pad3v5v] controls the device configuration. vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 idle 0v 1.2v internal reset generation module fsm v lvdhv3l 0v v lvdhv3h p1 ~1us table 20. pad3v5v field description value (1) 1. default manufacturing value before flash initialization is ?1? (3.3 v). description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v electrical characteristics spc560p44lx, spc560p50lx 66/112 doc id 14723 rev 9 3.10.2 dc electrical characteristics (5 v) ta ble 21 gives the dc electrical characteristics at 5 v (4.5 v < v dd_hv_iox < 5.5 v, nvusro[pad3v5v] = 0); see figure 14 . table 21. dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) symbol c parameter conditions value unit min max v il d low level input voltage ? ?0.1 (1) ?v p??0.35v dd_hv_iox v v ih p high level input voltage ?0.65v dd_hv_iox ?v d??v dd_hv_iox +0.1 (1) v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_iox ?v v ol_s p slow, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_s p slow, high level output voltage i oh =?3ma 0.8v dd_hv_iox ?v v ol_m p medium, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_m p medium, high level output voltage i oh =?3ma 0.8v dd_hv_iox ?v v ol_f p fast, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_f p fast, high level output voltage i oh =?3ma 0.8v dd_hv_iox ?v v ol_sym p symmetric, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_sym p symmetric, high level output voltage i oh =?3ma 0.8v dd_hv_iox ?v i pu p equivalent pull-up current v in =v il ?130 ? a v in =v ih ? ?10 i pd p equivalent pull-down current v in =v il 10 ? a v in =v ih ? 130 i il p input leakage current (all bidirectional ports) t a = ?40 to 125 c ?1 1 a i il p input leakage current (all adc input- only ports) t a = ?40 to 125 c ?0.5 0.5 a c in d input capacitance ? ? 10 pf i pu d reset , equivalent pull-up current v in =v il ?130 ? a v in =v ih ? ?10 1. ?sr? parameter values must not exceed the absolute maximum ratings shown in table 9 . spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 67/112 3.10.3 dc electrical characteristics (3.3 v) ta ble 23 gives the dc electrical characteristics at 3.3 v (3.0 v < v dd_hv_iox < 3.6 v, nvusro[pad3v5v] = 1); see figure 14 . table 22. supply current (5.0 v, nvusro[pad3v5v] = 0) symbol c parameter conditions value unit typ max i dd_lv_corx t supply current run?maximum mode (1) v dd_lv_corx externally forced at 1.3 v 40 mhz 62 77 ma 64 mhz 71 88 run?typical mode (2) 40 mhz 45 56 64 mhz 52 65 p run?maximum mode (3) v dd_lv_corx externally forced at 1.3 v 64 mhz 60 75 halt mode (4) v dd_lv_corx externally forced at 1.3 v ?1.510 stop mode (5) v dd_lv_corx externally forced at 1.3 v ?110 i dd_flash t flash during read v dd_hv_fl at 5.0 v ? 10 12 flash during erase operation on 1 flash module v dd_hv_fl at 5.0 v ? 15 19 i dd_adc t adc?maximum mode (1) v dd_hv_adc0 at 5.0 v v dd_hv_adc1 at 5.0 v f adc = 16mhz adc_1 3.5 5 adc_0 3 4 adc?typical mode (2) adc_1 0.8 1 adc_0 0.005 0.006 i dd_osc t oscillator v dd_osc at 5.0 v 8 mhz 2.6 3.2 1. maximum mode: flexpwm, adcs, ctu, dspi, linflex, flexcan, 15 output pins, 1st and 2nd pll enabled. i/o supply current excluded. 2. typical mode configurations: dspi, linflex, flexcan, 15 output pins, 1st pll only. i/o supply current excluded. 3. code fetched from ram, pll_0: 64 mhz system clock (x4 multiplier with 16 mhz xtal), pll_1 is on at phi_div2 = 120 mhz and phi_div3 = 80 mhz, auxiliary clock sour ces set that all peripherals receive maximum frequency, all peripherals enabled. 4. halt mode configurations: code fetc hed from ram, code and data flash memori es in low power mode, osc/pll_0/pll_1 are off, core clock frozen, all peripherals are disabled. 5. stop ?p? mode device under test (dut) configuration: code fetched from ram, code and data flash memories off, osc/pll_0/pll_1 are off, core clock frozen, all peripherals are disabled. table 23. dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) (1) symbol c parameter conditions value unit min max v il d low level input voltage ? ?0.1 (2) ?v p??0.35v dd_hv_iox v electrical characteristics spc560p44lx, spc560p50lx 68/112 doc id 14723 rev 9 v ih p high level input voltage ?0.65v dd_hv_iox ?v d??v dd_hv_iox +0.1 (2) v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_iox ?v v ol_s p slow, low level output voltage i ol = 1.5 ma ? 0.5 v v oh_s p slow, high level output voltage i oh =?1.5ma v dd_hv_iox ?0.8 ? v v ol_m p medium, low level output voltage i ol =2ma ? 0.5 v v oh_m p medium, high level output voltage i oh =?2ma v dd_hv_iox ?0.8 ? v v ol_f p fast, low level output voltage i ol = 1.5 ma ? 0.5 v v oh_f p fast, high level output voltage i oh =?1.5ma v dd_hv_iox ?0.8 ? v v ol_sym p symmetric, low level output voltage i ol = 1.5 ma ? 0.5 v v oh_sym p symmetric, high level output voltage i oh =?1.5ma v dd_hv_iox ?0.8 ? v i pu p equivalent pull-up current v in =v il ?130 ? a v in =v ih ? ?10 i pd p equivalent pull-down current v in =v il 10 ? a v in =v ih ? 130 i il p input leakage current (all bidirectional ports) t a = ?40 to 125 c ? 1 a i il p input leakage current (all adc input- only ports) t a = ?40 to 125 c ? 0.5 a c in d input capacitance ? ? 10 pf i pu d reset , equivalent pull-up current v in =v il ?130 ? a v in =v ih ? ?10 1. these specifications are design targets and subject to change per device characterization. 2. ?sr? parameter values must not exceed the absolute maximum ratings shown in table 9 . table 23. dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) (1) (continued) symbol c parameter conditions value unit min max spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 69/112 3.10.4 input dc electrical characteristics definition figure 14 shows the dc electrical characteristics behavior as function of time. table 24. supply current (3.3 v, nvusro[pad3v5v] = 1) symbol c parameter conditions value unit typ max i dd_lv_corx t supply current run?maximum mode (1) v dd_lv_corx externally forced at 1.3 v 40 mhz 62 77 ma 64 mhz 71 89 run?typical mode (2) 40 mhz 45 56 64 mhz 53 66 p run?maximum mode (3) v dd_lv_corx externally forced at 1.3 v 64 mhz 60 75 halt mode (4) v dd_lv_corx externally forced at 1.3 v ?1.510 stop mode (5) v dd_lv_corx externally forced at 1.3 v ?110 i dd_flash t flash during read on single mode v dd_hv_fl at 3.3 v ? 8 10 flash during erase operation on single mode v dd_hv_fl at 3.3 v ? 10 12 i dd_adc t adc?maximum mode (1) v dd_hv_adc0 at 3.3 v v dd_hv_adc1 at 3.3 v f adc =16mhz adc_1 2.5 4 adc_0 2 4 adc?typical mode (2) adc_1 0.8 1 adc_0 0.005 0.006 i dd_osc t oscillator v dd_osc at 3.3 v 8 mhz 2.4 3 1. maximum mode: flexpwm, adcs, ctu, dspi, linflex, flexcan, 15 output pins, 1st and 2nd pll enabled. i/o supply current excluded. 2. typical mode: dspi, linflex, flexcan, 15 output pins, 1st pll only. i/o supply current excluded. 3. code fetched from ram, pll_0: 64 mhz system clock (x4 multiplier with 16 mhz xtal), pll_1 is on at phi_div2 = 120 mhz and phi_div3 = 80 mhz, auxiliary clock source s set that all peripherals receive maximum frequency, all peripherals enabled. 4. halt mode configurations: code fetc hed from ram, code and data flash memori es in low power mode, osc/pll_0/pll_1 are off, core clock frozen, all peripherals are disabled. 5. stop ?p? mode device under test (dut) configuration: code fetched from ram, code and data flash memories off, osc/pll_0/pll_1 are off, core clock frozen, all peripherals are disabled. electrical characteristics spc560p44lx, spc560p50lx 70/112 doc id 14723 rev 9 figure 14. input dc electrical characteristics definition 3.10.5 i/o pad current specification the i/o pads are distributed across the i/o supply segment. each i/o supply segment is associated to a v dd /v ss supply pair as described in ta ble 25 . ta ble 26 provides the weight of concurrent switching i/os. in order to ensure device functionality, the sum of the weight of concurrent switching i/os on a single segment should remain below 100%. v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0? table 25. i/o supply segment package supply segment 12345 6 7 lqfp144 pin8 ? pin20 pin23 ? pin38 pin39 ? pin55 pin58 ? pin68 pin73 ? pin89 pin92 ? pin125 pin128 ? pin5 lqfp100 pin15 ? pin26 pin27 ? pin38 pin41 ? pin46 pin51 ? pin61 pin64 ? pin86 pin89 ? pin10 ? table 26. i/o weight pad lqfp144 lqfp100 weight 5v weight 3.3v weight 5v weight 3.3v nmi1%1%1%1% pad[6] 6% 5% 14% 13% pad[49] 5% 4% 14% 12% pad[84] 14% 10% ? ? pad[85] 9% 7% ? ? spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 71/112 pad[86] 9% 6% ? ? modo[0] 12% 8% ? ? pad[7] 4% 4% 11% 10% pad[36] 5% 4% 11% 9% pad[8] 5% 4% 10% 9% pad[37] 5% 4% 10% 9% pad[5] 5% 4% 9% 8% pad[39]5%4%9%8% pad[35]5%4%8%7% pad[87] 12% 9% ? ? pad[88] 9% 6% ? ? pad[89] 10% 7% ? ? pad[90] 15% 11% ? ? pad[91] 6% 5% ? ? pad[57]8%7%8%7% pad[56] 13% 11% 13% 11% pad[53] 14% 12% 14% 12% pad[54] 15% 13% 15% 13% pad[55] 25% 22% 25% 22% pad[96] 27% 24% ? ? pad[65]1%1%1%1% pad[67] 1% 1% ? ? pad[33]1%1%1%1% pad[68] 1% 1% ? ? pad[23]1%1%1%1% pad[69] 1% 1% ? ? pad[34]1%1%1%1% pad[70] 1% 1% ? ? pad[24]1%1%1%1% pad[71] 1% 1% ? ? pad[66]1%1%1%1% pad[25]1%1%1%1% pad[26]1%1%1%1% table 26. i/o weight (continued) pad lqfp144 lqfp100 weight 5v weight 3.3v weight 5v weight 3.3v electrical characteristics spc560p44lx, spc560p50lx 72/112 doc id 14723 rev 9 pad[27]1%1%1%1% pad[28]1%1%1%1% pad[63]1%1%1%1% pad[72] 1% 1% ? ? pad[29]1%1%1%1% pad[73] 1% 1% ? ? pad[31]1%1%1%1% pad[74] 1% 1% ? ? pad[30]1%1%1%1% pad[75] 1% 1% ? ? pad[32]1%1%1%1% pad[76] 1% 1% ? ? pad[64]1%1%1%1% pad[0] 23% 20% 23% 20% pad[1] 21% 18% 21% 18% pad[107] 20% 17% ? ? pad[58] 19% 16% 19% 16% pad[106] 18% 16% ? ? pad[59] 17% 15% 17% 15% pad[105] 16% 14% ? ? pad[43] 15% 13% 15% 13% pad[104] 14% 13% ? ? pad[44] 13% 12% 13% 12% pad[103] 12% 11% ? ? pad[2] 11% 10% 11% 10% pad[101] 11% 9% ? ? pad[21] 10% 8% 10% 8% tms1%1%1%1% tck1%1%1%1% pad[20] 16% 11% 16% 11% pad[3] 4% 3% 4% 3% pad[61]9%8%9%8% pad[102] 11% 10% ? ? table 26. i/o weight (continued) pad lqfp144 lqfp100 weight 5v weight 3.3v weight 5v weight 3.3v spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 73/112 pad[60] 11% 10% 11% 10% pad[100] 12% 10% ? ? pad[45] 12% 10% 12% 10% pad[98] 12% 11% ? ? pad[46] 12% 11% 12% 11% pad[99] 13% 11% ? ? pad[62] 13% 11% 13% 11% pad[92] 13% 12% ? ? vpp_test 1% 1% 1% 1% pad[4] 14% 12% 14% 12% pad[16] 13% 12% 13% 12% pad[17] 13% 11% 13% 11% pad[42] 13% 11% 13% 11% pad[93] 12% 11% ? ? pad[95] 12% 11% ? ? pad[18] 12% 10% 12% 10% pad[94] 11% 10% ? ? pad[19] 11% 10% 11% 10% pad[77] 10% 9% ? ? pad[10] 10% 9% 10% 9% pad[78] 9% 8% ? ? pad[11]9%8%9%8% pad[79] 8% 7% ? ? pad[12]7%7%7%7% pad[41]7%6%7%6% pad[47]5%4%5%4% pad[48]4%4%4%4% pad[51]4%4%4%4% pad[52]5%4%5%4% pad[40]5%5%6%5% pad[80] 9% 8% ? ? pad[9] 10% 9% 11% 10% pad[81] 10% 9% ? ? table 26. i/o weight (continued) pad lqfp144 lqfp100 weight 5v weight 3.3v weight 5v weight 3.3v electrical characteristics spc560p44lx, spc560p50lx 74/112 doc id 14723 rev 9 pad[13] 10% 9% 12% 11% pad[82] 10% 9% ? ? pad[22] 10% 9% 13% 12% pad[83] 10% 9% ? ? pad[50] 10% 9% 14% 12% pad[97] 10% 9% ? ? pad[38] 10% 9% 14% 13% pad[14] 9% 8% 14% 13% pad[15] 9% 8% 15% 13% table 26. i/o weight (continued) pad lqfp144 lqfp100 weight 5v weight 3.3v weight 5v weight 3.3v table 27. i/o consumption symbol c parameter conditions (1) value unit min typ max i swtslw (2) cc d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??20 ma v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed (2) cc d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??29 ma v dd = 3.3 v 10%, pad3v5v = 1 ??17 i swtfst (2) cc d dynamic i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??110 ma v dd = 3.3 v 10%, pad3v5v = 1 ??50 i rmsslw cc d root medium square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3 ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 75/112 3.11 main oscillator electrical characteristics the spc560p44lx, spc560p50lx provides an oscillator/resonator driver. i rmsmed cc d root medium square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6 ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11 i rmsfst cc d root medium square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22 ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 56 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 35 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified 2. stated maximum values represent peak consumption that lasts only a few ns during i/o transition. table 27. i/o consumption (continued) symbol c parameter conditions (1) value unit min typ max table 28. main oscillator output electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) symbol c parameter value unit min max f osc sr ? oscillator frequency 440mhz g m ?p transconduc tance 6.5 25 ma/v v osc ?t oscillation amplitude on xtal pin 1?v t oscsu ?t start-up time (1),(2) 1. the start-up time is dependent upon crystal characteristics, board leakage, etc., high esr and excessive capacitive loads can cause long start-up time. 2. value captured when amplitude reaches 90% of xtal 8?ms electrical characteristics spc560p44lx, spc560p50lx 76/112 doc id 14723 rev 9 3.12 fmpll electrical characteristics table 29. main oscillator output electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) symbol c parameter value unit min max f osc sr ? oscillator frequency 4 40 mhz g m ? p transconductance 4 20 ma/v v osc ? t oscillation amplitude on xtal pin 1 ? v t oscsu ? t start-up time (1),(2) 1. the start-up time is dependent upon crystal characteristics, board leakage, etc., high esr and excessive capacitive loads can cause long start-up time. 2. value captured when amplitude reaches 90% of xtal 8?ms table 30. input clock characteristics symbol parameter value unit min typ max f osc sr oscillator frequency 4 ? 40 mhz f clk sr frequency in bypass ? ? 64 mhz t rclk sr rise/fall time in bypass ? ? 1 ns t dc sr duty cycle 47.5 50 52.5 % table 31. fmpll electrical characteristics symbol c parameter conditions (1) value unit min max f ref_crystal f ref_ext d pll reference frequency range (2) crystal reference 4 40 mhz f pllin d phase detector input frequency range (after pre-divider) ?416mhz f fmpllout d clock frequency range in normal mode ? 16 120 mhz f free p free-running frequency measured using clock division ? typically /16 20 150 mhz t cyc d system clock period ? ? 1 / f sys ns f lorl f lorh d loss of reference frequency window (3) lower limit 1.6 3.7 mhz upper limit 24 56 f scm d self-clocked mode frequency (4),(5) ?20150mhz spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 77/112 c jitter t clkout period jitter (6),(7),(8),(9) short-term jitter (10) f sys maximum ? 44%f clkout long-term jitter (avg. over 2 ms interval) f pllin = 16 mhz (resonator) , f pllclk at 64 mhz, 4000 cycles ?10 ns t lpll d pll lock time (11), (12) ??200s t dc d duty cycle of reference ?4060% f lck d frequency lock range ? ? 66% f sys f ul d frequency un-lock range ? -18 18 % f sys f cs f ds d modulation depth center spread 0.25 4.0 (13) % f sys down spread ? 0.5 ? 8.0 f mod d modulation frequency (14) ??70khz 1. v dd_lv_corx = 1.2 v 10%; v ss = 0 v; t a = ?40 to 125 c, unless otherwise specified 2. considering operation with pll not bypassed 3. ?loss of reference frequency? window is the reference fr equency range outside of which the pll is in self-clocked mode. 4. self-clocked mode frequency is the frequency that the pll operates at when the reference frequency falls outside the f lor window. 5. f vco self clock range is 20?150 mhz. f scm represents f sys after pll output divider (erfd) of 2 through 16 in enhanced mode. 6. this value is determined by the crystal manufacturer and board design. 7. jitter is the average deviation from the programmed frequency meas ured over the specified interval at maximum f sys . measurements are made with the device pow ered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 8. proper pc board layout procedures must be followed to achieve specifications. 9. values are with frequency modulation disabled. if fr equency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 10. short term jitter is measured on the clock rising edge at cycle n and cycle n+4. 11. this value is determined by the crystal manufacturer and boar d design. for 4 mhz to 20 mhz crystals specified for this pll, load capacitors should not exceed these limits. 12. this specification applies to the period required for the p ll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 13. this value is true when operating at frequencies above 60 mhz, otherwise f cs is 2% (above 64 mhz). 14. modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 khz. table 31. fmpll electrical characteristics (continued) symbol c parameter conditions (1) value unit min max electrical characteristics spc560p44lx, spc560p50lx 78/112 doc id 14723 rev 9 3.13 16 mhz rc oscillator electrical characteristics 3.14 analog-to-digital converter (adc) electrical characteristics the device provides a 10-bit successive approximation register (sar) analog-to-digital converter. table 32. 16 mhz rc oscillator electrical characteristics symbol c parameter conditions value unit min typ max f rc p rc oscillator frequency t a = 25 c ? 16 ? mhz rcmvar p fast internal rc oscillator variation over temperature and supply with respect to f rc at t a = 25 c in high- frequency configuration ??5?5% rcmtrim t post trim accuracy: the variation of the ptf (1) from the 16 mhz t a = 25 c ?1 ? 1 % rcmstep t fast internal rc oscillator trimming step t a = 25 c ? 1.6 ? % 1. ptf = post trimming frequency: the frequency of the output clock after trimming at typical supply voltage and temperature spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 79/112 figure 15. adc characteristics and error definitions 3.14.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high- impedance source. a real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the source impedance value of the transducer or circuit supplying the analog signal to be measured. (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve 1 lsb ideal = v dd_adc / 1024 v in(a) (lsb ideal ) code out electrical characteristics spc560p44lx, spc560p50lx 80/112 doc id 14723 rev 9 the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: c s and c p2 being substantially two switched capacitances, with a frequency equal to the adc conversion rate, it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 1 mhz, with c s +c p2 equal to 3 pf, a resistance of 330 k is obtained (r eq = 1 / (fc (c s +c p2 )), where fc represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s +c p2 ) and the sum of r s + r f , the external circuit must be designed to respect the equation 4 : equation 4 equation 4 generates a constraint for external network design, in particular on resistive path. figure 16. input equivalent circuit v a r s r f + r eq --------------------- ? 1 2 -- -lsb < r f c f r s r l r sw1 c p2 c s v dd sampling source filter current limiter external circuit internal circuit scheme c p1 r ad channel selection v a r s : source impedance r f : filter resistance c f : filter capacitance r l : current limiter resistance r sw1 : channel selection switch impedance r ad : sampling switch impedance c p : pin capacitance (two contributions, c p1 and c p2 ) c s : sampling capacitance spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 81/112 a second aspect involving the capacitance network shall be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 16 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch closed). figure 17. transient behavior during sampling phase in particular two different transient periods can be distinguished: a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is equation 5 equation 5 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: equation 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : v a v a1 v a2 t t s v cs voltage transient on c s v < 0.5 lsb 1 2 1 < (r sw + r ad ) c s << t s 2 = r l (c s + c p1 + c p2 ) 1 r sw r ad + () = c p c s ? c p c s + --------------------- ? 1 r sw r ad + () < c s t s ? ? electrical characteristics spc560p44lx, spc560p50lx 82/112 doc id 14723 rev 9 equation 7 a second charge transfer involves also c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: equation 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: equation 9 of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): equation 10 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing. figure 18. spectral representation of input signal v a1 c s c p1 c p2 ++ () ? v a c p1 c p2 + () ? = 2 r l < c s c p1 c p2 ++ () ? 8.5 2 ? 8.5 r l c s c p1 c p2 ++ () ? ? =t s < v a2 c s c p1 c p2 c f +++ () ? v a c f ? v a1 +c p1 c p2 +c s + () ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c 2 r f c f (conversion rate vs. filter pole) noise spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 83/112 calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : equation 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: equation 12 3.14.2 adc conversion characteristics v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? > table 33. adc conversion characteristics symbol c parameter conditions (1) value unit min typ max v inan0 sr adc0 and shared adc0/1 analog input voltage (2), (3) ? v ss_hv_adv0 ? 0.3 ? v dd_hv_adv0 + 0.3 v v inan1 sr adc1 analog input voltage (2), (4) ? v ss_hv_adv1 ? 0.3 ? v dd_hv_adv1 + 0.3 v f ck sr ? adc clock frequency (depends on adc configuration) (the duty cycle depends on ad_clk (5) frequency) ?3 (6) ?60mhz f s sr ? sampling frequency ? ? ? 1.53 mhz t adc_s ? d sample time (7) f adc = 20 mhz, inpsamp = 3 125 ? ? ns f adc = 9 mhz, inpsamp = 255 ? ? 28.2 s t adc_c ? p conversion time (8) f adc = 20 mhz (9) , inpcmp = 1 0.650 ? ? s electrical characteristics spc560p44lx, spc560p50lx 84/112 doc id 14723 rev 9 t adc_pu sr ? adc power-up delay (time needed for adc to settle exiting from software power down; pwdn bit = 0) ???1.5s c s (10) ?d adc input sampling capacitance ???2.5pf c p1 (10) ? d adc input pin capacitance 1 ? ? ? 3 pf c p2 (10) ? d adc input pin capacitance 2 ? ? ? 1 pf r sw1 (10) ?d internal resistance of analog source v dd_hv_adc = 5v10% ??0.6k v dd_hv_adc = 3.3 v 10% ??3k r ad (10) ?d internal resistance of analog source ???2k i inj ? t input current injection current injection on one adc input, different from the converted one. remains within tue spec. ?5 ? 5 ma inl cc p integral non-linearity no overload ?1.5 ? 1.5 lsb dnl cc p differential non-linearity no overload ?1.0 ? 1.0 lsb ose cc t offset error ? ? 1 ? lsb ge cc t gain error ? ? 1 ? lsb tue cc p total unadjusted error without current injection ? ?2.5 ? 2.5 lsb tue cc t total unadjusted error with current injection ??3?3lsb 1. v dd = 3.3 v to 3.6 v / 4.5 v to 5.5 v, t a = ?40 c to t a max , unless otherwise specified and analog input voltage from v ss_hv_adcx to v dd_hv_adcx . 2. v ainx may exceed v ss_hv_ad and v dd_hv_ad limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped res pectively to 0x000 or 0x3ff. 3. not allowed to refer this voltage to v dd_hv_adv1 , v ss_hv_adv1 4. not allowed to refer this voltage to v dd_hv_adv0 , v ss_hv_adv0 5. ad_clk clock is always half of the adc module input clock defined via the auxiliary clock divider for the adc. 6. when configured to allow 60 mhz adc, the minimum adc clock speed is 9 mhz, below which precision is lost. 7. during the sample time the input capacitance cs can be charged/discharged by the exter nal source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 8. this parameter includes the sample time t adc_s . 9. 20 mhz adc clock. specific prescaler is programm ed on mc_pll_clk to provide 20 mhz clock to the adc. 10. see figure 16 . table 33. adc conversion characteristics (continued) symbol c parameter conditions (1) value unit min typ max spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 85/112 3.15 flash memory electrical characteristics table 34. program and erase specifications symbol c parameter value unit min typical (1) initial max (2) max (3) t dwprogram p double word (64 bits) program time (4) ?2250500s t bkprg p bank program (512 kb) (4)(5) ? 1.45 1.65 33 s p bank program (64 kb) (4)(5) ? 0.18 0.21 4.10 s t 16kpperase p 16 kb block pre-program and erase time ? 300 500 5000 ms t 32kpperase p 32 kb block pre-program and erase time ? 400 600 5000 ms t 128kpperase p 128 kb block pre-program and erase time ? 800 1300 7500 ms 1. typical program and erase times assume nominal supply valu es and operation at 25 c. a ll times are subject to change pending device characterization. 2. initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. 3. the maximum program and erase times occur after the specif ied number of program/erase cycles. these maximum values are characterized but not guaranteed. 4. actual hardware programming times. th is does not include software overhead. 5. typical bank programming time assumes that all cells are progr ammed in a single pulse. in reality some cells will require more than one pulse, adding a small overhead to total bank programming time (see initial max column). table 35. flash memory module life symbol c parameter conditions value unit min typ p/e c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100000 ? cycles p/e c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ? 10000 100000 cycles p/e c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ? 1000 100000 cycles retention c minimum data retention at 85 c average ambient temperature (1) blocks with 0?1000 p/e cycles 20 ? years blocks with 10000 p/e cycles 10 ? years blocks with 100000 p/e cycles 5?years 1. ambient temperature averaged over dur ation of application, not to exceed recommended product operating temperature range. electrical characteristics spc560p44lx, spc560p50lx 86/112 doc id 14723 rev 9 3.16 ac specifications 3.16.1 pad ac specifications table 36. flash memory read access timing symbol c parameter conditions (1) max value unit f max c maximum working frequency at given number of wait states in worst conditions 2 wait states 66 mhz 0 wait states 18 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified table 37. output pin transition times symbol c parameter conditions (1) value unit min typ max t tr cc d output transition time output pin (2) slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ??40 tc l = 50 pf ? ? 50 dc l = 100 pf ? ? 75 t tr cc d output transition time output pin (2) medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ??10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 t tr cc d output transition time output pin (2) fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ?? 4 ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 t sym (3) cc t symmetric transition time, same drive strength between n and p transistor v dd = 5.0 v 10%, pad3v5v = 0 ? ? 4 ns v dd = 3.3 v 10%, pad3v5v = 1 ? ? 5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 c to t a max , unless otherwise specified 2. c l includes device and package capacitances (c pkg < 5 pf). 3. transition timing of both positive and negative slopes will differ maximum 50% spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 87/112 figure 19. pad output delay 3.17 ac timing characteristics 3.17.1 reset pin characteristics the spc560p44lx, spc560p50lx implements a dedicated bidirectional reset pin. figure 20. start-up reset requirements v dd_hv_iox /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output v il v dd device reset forced by v reset v ddmin v reset v ih device start-up phase t por electrical characteristics spc560p44lx, spc560p50lx 88/112 doc id 14723 rev 9 figure 21. noise filtering on reset signal v r e s e t v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset table 38. reset electrical characteristics symbol c parameter conditions (1) value unit min typ max v ih sr p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ?0.4 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol cc p output low level push pull, i ol = 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v push pull, i ol = 1ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd push pull, i ol = 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 89/112 3.17.2 ieee 1149.1 interface timing t tr cc d output transition time output pin (3) medium configuration c l = 25pf, v dd = 5.0 v 10%, pad3v5v = 0 ??10 ns c l = 50pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20 c l = 100pf, v dd = 5.0 v 10%, pad3v5v = 0 ??40 c l = 25pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 c l = 50pf, v dd = 3.3 v 10%, pad3v5v = 1 ??25 c l = 100pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 w frst sr p reset input filtered pulse ???40ns w nfrst sr p reset input not filtered pulse ? 500 ? ? ns t por cc d maximum delay before internal reset is released after all v dd_hv reach nominal supply monotonic v dd_hv supply ramp ? ? 1 ms |i wpu |ccp weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 v dd = 5.0 v 10%, pad3v5v = 1 (4) 10 ? 250 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 c to t a max , unless otherwise specified 2. this is a transient configuration during power-up, up to the end of reset phase2 (refer to rgm module section of device reference manual). 3. c l includes device and package capacitance (c pkg <5pf). 4. the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration dur ing power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 38. reset electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max table 39. jtag pin ac electrical characteristics no. symbol c parameter conditions value unit min max 1t jcyc cc d tck cycle time ? 100 ? ns 2t jdc cc d tck clock pulse width (measured at v dd_hv_iox /2) ? 40 60 ns 3t tckrise cc d tck rise and fall times (40% ? 70%) ? ? 3 ns 4t tmss, t tdis cc d tms, tdi data setup time ? 5 ? ns electrical characteristics spc560p44lx, spc560p50lx 90/112 doc id 14723 rev 9 figure 22. jtag test clock input timing 5t tmsh, t tdih cc d tms, tdi data hold time ? 25 ? ns 6t tdov cc d tck low to tdo data valid ? ? 40 ns 7t tdoi cc d tck low to tdo data invalid ? 0 ? ns 8t tdohz cc d tck low to tdo high impedance ? 40 ? ns 11 t bsdv cc d tck falling edge to output valid ? ? 50 ns 12 t bsdvz cc d tck falling edge to output valid out of high impedance ??50ns 13 t bsdhz cc d tck falling edge to output high impedance ? ? 50 ns 14 t bsdst cc d boundary scan input valid to tck rising edge ? 50 ? ns 15 t bsdht cc d tck rising edge to boundary scan input invalid ? 50 ? ns table 39. jtag pin ac electrical characteristics (continued) no. symbol c parameter conditions value unit min max tck 1 2 2 3 3 spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 91/112 figure 23. jtag test access port timing tck 4 5 6 7 8 tms, tdi tdo electrical characteristics spc560p44lx, spc560p50lx 92/112 doc id 14723 rev 9 figure 24. jtag boundary scan timing 3.17.3 nexus timing tck output signals input signals output signals 11 12 13 14 15 table 40. nexus debug port timing (1) no. symbol c parameter value unit min typ max 1t mcyc cc d mcko cycle time 32 ? ? ns 2t mdov cc d mcko low to mdo data valid (2) ??6ns 3t mseov cc d mcko low to mseo data valid (2) ??6ns 4t evtov cc d mcko low to evto data valid (2) ??6ns 5t tcyc cc d tck cycle time 64 (3) ??ns spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 93/112 figure 25. nexus output timing figure 26. nexus event trigger and test clock timings 6 t ntdis cc d tdi data setup time 6 ? ? ns t ntmss cc d tms data setup time 6 ? ? ns 7 t ntdih cc d tdi data hold time 10 ? ? ns t ntmsh cc d tms data hold time 10 ? ? ns 8t tdov cc d tck low to tdo data valid ? ? 35 ns 9t tdoi cc d tck low to tdo data invalid 6 ? ? ns 1. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. 2. mdo, mseo , and evto data is held valid until next mcko low cycle. 3. lower frequency is required to be fully compliant to standard. table 40. nexus debug port timing (1) (continued) no. symbol c parameter value unit min typ max 1 3 4 mcko mdo mseo evto output data valid 2 tck 5 evti evto electrical characteristics spc560p44lx, spc560p50lx 94/112 doc id 14723 rev 9 figure 27. nexus tdi, tms, tdo timing 3.17.4 external interrupt timing (irq pin) tdo 6 7 tms, tdi 8 tck 9 table 41. external interrupt timing (1) no. symbol c parameter conditions value unit min max 1t ipwl cc d irq pulse width low ? 4 ? t cyc 2t ipwh cc d irq pulse width high ? 4 ? t cyc 3t icyc cc d irq edge to edge time (2) ?4 + n (3) ?t cyc 1. irq timing specified at f sys = 64 mhz and v dd_hv_iox = 3.0 v to 5.5 v, t a = t l to t h , and c l = 200 pf with src = 0b00. 2. applies when irq pins are configured for rising edge or falling edge events, but not both. 3. n = isr time to clear the flag spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 95/112 figure 28. external interrupt timing 3.17.5 dspi timing irq 2 3 1 table 42. dspi timing (1) no. symbol c parameter conditions value unit min max 1t sck cc d dspi cycle time master (mtfe = 0) 60 ? ns slave (mtfe = 0) 60 ? 2t csc cc d cs to sck delay ? 16 ? ns 3t asc cc d after sck delay ? 26 ? ns 4t sdc cc d sck duty cycle ? 0.4 * t sck 0.6 * t sck ns 5t a cc d slave access time ss active to sout valid ? 30 ns 6t dis cc d slave sout disable time ss inactive to sout high impedance or invalid ?16ns 7t pcsc cc d pcsx to pcss time ? 13 ? ns 8t pasc cc d pcss to pcsx time ? 13 ? ns 9t sui cc d data setup time for inputs master (mtfe = 0) 35 ? ns slave 4 ? master (mtfe = 1, cpha = 0) 35 ? master (mtfe = 1, cpha = 1) 35 ? 10 t hi cc d data hold time for inputs master (mtfe = 0) ?5 ? ns slave 4 ? master (mtfe = 1, cpha = 0) 11 ? master (mtfe = 1, cpha = 1) ?5 ? electrical characteristics spc560p44lx, spc560p50lx 96/112 doc id 14723 rev 9 figure 29. dspi classic spi timing ? master, cpha = 0 11 t suo cc d data valid (after sck edge) master (mtfe = 0) ? 12 ns slave ? 36 master (mtfe = 1, cpha = 0) ? 12 master (mtfe = 1, cpha = 1) ? 12 12 t ho cc d data hold time for outputs master (mtfe = 0) ?2 ? ns slave 6 ? master (mtfe = 1, cpha = 0) 6 ? master (mtfe = 1, cpha = 1) ?2 ? 1. all timing is provided with 50 pf capacitance on output, 1 ns transition time on input signal. table 42. dspi timing (1) (continued) no. symbol c parameter conditions value unit min max data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 note : numbers shown reference table 42 . spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 97/112 figure 30. dspi classic spi timing ? master, cpha = 1 figure 31. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) note : numbers shown reference table 42 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) note : numbers shown reference table 42 . electrical characteristics spc560p44lx, spc560p50lx 98/112 doc id 14723 rev 9 figure 32. dspi classic spi timing ? slave, cpha = 1 figure 33. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note : numbers shown reference table 42 . pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) note : numbers shown reference table 42 . spc560p44lx, spc560p50lx electrical characteristics doc id 14723 rev 9 99/112 figure 34. dspi modified transfer format timing ? master, cpha = 1 figure 35. dspi modified transfer format timing ? slave, cpha = 0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) note : numbers shown reference table 42 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 note : numbers shown reference table 42 . electrical characteristics spc560p44lx, spc560p50lx 100/112 doc id 14723 rev 9 figure 36. dspi modified transfer format timing ? slave, cpha = 1 figure 37. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note : numbers shown reference table 42 . pcsx 7 8 pcss note : numbers shown reference table 42 . spc560p44lx, spc560p50lx package characteristics doc id 14723 rev 9 101/112 4 package characteristics 4.1 ecopack ? iin order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.2 package mechanical data 4.2.1 lqfp144 mechanical outline drawing l figure 38. lqfp144 package mechanical drawing d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a package characteristics spc560p44lx, spc560p50lx 102/112 doc id 14723 rev 9 table 43. lqfp144 mechanical data symbol dimensions mm inches (1) min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 ? 17.500 ? ? 0.6890 ? e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 ? 17.500 ? ? 0.6890 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 3.5 0.0 7.0 ccc (2) 0.080 0.0031 1. values in inches are converted from mil limeters (mm) and rounded to four decimal digits. 2. tolerance spc560p44lx, spc560p50lx package characteristics doc id 14723 rev 9 103/112 4.2.2 lqfp100 mechanical outline drawing figure 39. lqfp100 package mechanical drawing d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me package characteristics spc560p44lx, spc560p50lx 104/112 doc id 14723 rev 9 table 44. lqfp100 package mechanical data symbol dimensions mm inches (1) min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 ? 12.000 ? ? 0.4724 ? e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 ? 12.000 ? ? 0.4724 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 0.0 3.5 7.0 ccc (2) 0.08 0.0031 1. values in inches are converted from mil limeters (mm) and rounded to four decimal digits. 2. tolerance spc560p44lx, spc560p50lx ordering information doc id 14723 rev 9 105/112 5 ordering information figure 40. commercial product code structure (a) memory conditioning core family y = tray r = tape and reel x = tape and reel 90 a=64mhz, 5v b = 64 mhz, 3.3 v c=40mhz, 5v d = 40 mhz, 3.3 v f = full featured a = airbag e = data flash memory b = ?40 to 105 c c = ?40 to 125 c l3 = lqfp100 l5 = lqfp144 50 = 512 kb 44 = 384 kb p = spc560px family 0 = e200z0 spc56 = power architecture in 90 nm temperature package custom vers. spc56 50 y 0p c l5 efa example code: product identifier a. not all configurations are available on the market. please contact your st sales repres entative to get the list of orderable commercial part number. abbreviations spc560p44lx, spc560p50lx 106/112 doc id 14723 rev 9 appendix a abbreviations ta ble 45 lists abbreviations used in this document. table 45. abbreviations abbreviation meaning cmos complementary metal?oxide?semiconductor cpha clock phase cpol clock polarity cs peripheral chip select dut device under test ecc error code correction evto event out gpio general purpose input/output mc modulus counter mcko message clock out mcu microcontroller unit mdo message data out mseo message start/end out mtfe modified timing format enable npn negative-positive-negative nvusro non-volatile user options register ptf post trimming frequency pwm pulse width modulation rbw resolution bandwidth sck serial communications clock sout serial data out tck test clock input tdi test data input tdo test data output tms test mode select spc560p44lx, spc560p50lx revision history doc id 14723 rev 9 107/112 6 revision history ta ble 46 summarizes revisions to this document. table 46. revision history date revision changes 28-aug-2008 1 initial release 25-nov-2008 2 table 7 : tdo and tdi pins (port pins b[4:5] are single function pins. table 12 , table 13 : thermal characteristics added. table 11 , table 12 : emi testing specifications split into separate tables for normal mode and airbag mode; data to be added in a later revision. table 16 , table 17 , table 19 , table 20 : supply current specifications split into separate tables for normal mode and airbag mode; data to be added in a later revision. table 23 : values for i ol and i oh (in conditions column) changed. max values for v oh_s , v oh_m , v oh_f and v oh_sym deleted. v ilr max value changed. i pur min and max values changed. table 27 : sensitivity value changed. table 30 : most values in table changed. 05-mar-2009 3 description of system requirements, controller characteristics and how controller characteristics are guaranteed updated. electrical parameters updated. emi characteristics are now in one table; values have been updated. esd characteristics are now in one table. electrical parameters are identified as either system requirements or controller characteristics. method used to guarantee each controller characteristic is noted in table. ac timings: 1149.1 (jtag) timing, nexus timing, external interrupt timing, and dspi timing sections deleted revision history spc560p44lx, spc560p50lx 108/112 doc id 14723 rev 9 07-jul-2009 4 through all document: ? replaced all ?reset_b? occurrences with ?reset? through all document. ? ac timings: 1149.1 (jtag) timing, nexus timing, external interrupt timing, and dspi timing sections inserted again. ? electrical parameters updated. section , features : ? specified lin 2.1 in communications interfaces feature. table 2 ? added row for data flash. table 4 ? added a footnote regarding the decoupling capacitors. table 6 ? removed the ?other function? column. ? rearranged the contents. table 14 ? updated definition of condition column. table 19 ? merged in an unique table the power consumption data related to "maximum mode" and "airbag mode". table 21 ? merged in an unique table the power consumption data related to "maximum mode" and "airbag mode". table 29 ? updated the parameter definition of rcmvar. ? removed the condition definition of rcmvar. table 29 ? added t adc_c and tue rows. table 30 ? added t adc_c and tue rows. ? removed r sw2. table 33 ? added. table 29 ? updated and added footnotes. section 3.16.1 reset pin characteristics ? replaces whole section. table 38 ? renamed the ?flash (kb)? heading column in ?code flash / data flash (ee) (kb)? ? replaced the value of ram from 32 to 36kb in the last four rows. table 46. revision history (continued) date revision changes spc560p44lx, spc560p50lx revision history doc id 14723 rev 9 109/112 27-oct-2009 5 - added ?full feature? and ?airbag? customization. - removed b[4] and b[5] rows from ?pin muxing? table and inserted them on ?system pins? table. - updated package pinout. - rewrote entirely section ?power up/dpwn sequencing? section. - renamend ?v dd_lv_pll ? and ?v ss_lv_pll ? supply pins with respectively ?v dd_lv_cor3 ? and ?v ss_lv_cor3?. - added explicative figures on ?electrical characteristics? section. - updated ?thermal characteristics? for 100-pin. - proposed two different configuration of ?voltage regulator. - inserted power up/down sequence. - added explicative figures on ?dc electrical characteristics?. - added ?i/o pad current specification? section. - renamed the ?airbag mode? with ?typical mode?and updated the values on ?supply current? tables. - added more order code. 06-apr-2010 6 inserted label of y-axis in the ?independent adc supply? figure. ?recommended operating conditions? tables: moved the t j row to ?absolute maximum ratings? table. rewrite note 1 and 3 inverted min a typ value of c dec2 on ?voltage regulator electrical characteristics? table. removed an useless duplicate of ?voltage regulator electrical characteristics? table. inserted the name of c s into ?input equivalent circuit? figure. removed leakage ivpp from datasheet. updated ?supply current? tables. added note on ?output pin transition times? table. updated ?temperature sensor electrical characteristics? table. updated ?16 mhz rc oscillator electrical characteristics? table. removed the note about the condition from ?flash read access timing? table. removed the notes that assert the values need to be confirmed before validation. 07-apr-2011 7 formatting and editorial changes throughout removed all content referencing junction temperature sensor cover page features: ? cpu core?specified 64 mhz frequency ? updated memory features ? etimer units: changed ?up/down capabilities? to ?up/down count capabilities? ? adc?changed ?2 13 input channels? to ?2 11 input channels, + 4 shared channels? ? replaced ?on-chip can/uart/flexray bootstrap loader? with ?on-chip can/uart bootstrap loader? section 1: introduction : changed title (was: overview); reorganized contents spc560p44lx, spc560p50lx device comparison: ? adc feature: changed ?16 channels? to ?15-channel?; added footnote to to indicate that four channels are shared between the two adcs ? removed spc560p40 column ? changed ?dual channel? to ?selectable single or dual channel support? in flexray footnote ? updated ?etimer? feature ? updated footnote relative to ?digital power supply? feature table 46. revision history (continued) date revision changes revision history spc560p44lx, spc560p50lx 110/112 doc id 14723 rev 9 07-apr-2011 7 (cont?d) spc560p44lx, spc560p50lx device configuration differences: removed ?temperature? row (temperature information is provided in order codes) updated spc560p44lx, spc560p50lx block diagram added spc560p44lx, spc560p50lx series block summary added section 1.5 feature details section 2.1, package pinouts : removed alternate functions from pinout diagrams supply pins: updated descriptions of power supply pins (1.2 v) system pins: updated table pin muxing: added rows ?b[4]? and ?b[5] section 3.3, absolute maximum ratings : added voltage specifications to titles of figure 5 and figure 6 ; in table 9 , changed row ?v ss_hv / digital ground? to ?v ss / device ground?; updated symbols section 3.4, recommended operating conditions : added voltage specifications to titles of figure 7 and figure 8 recommended operating conditions (5.0 v), and recommended operating conditions (3.3 v): changed row ?v ss_hv / digital ground? to ?v ss / device ground?; updated symbols updated section 3.5.1, package thermal characteristics updated section 3.6, electromagnetic interference (emi) characteristics section 3.8.1, voltage regulator electrical characteristics : amended titles of table 16 and table 19 voltage regulator electrical characteristics (configuration without resistor on base) and voltage regulator electrical characteristics (configuration with resistor on base): updated symbol and values for v dd_lv_regcor low voltage monitor electrical characteristics: updated v mlvddok_h max value?was 1.15 v; is 1.145 v section 3.10, dc electrical characteristics : reorganized contents updated section 3.10.1, nvusro register (includes adding section nvusro[oscillator_margin] field description ) supply current (5.0 v, nvusro[pad3v5v] = 0): updated symbols corrected parameter descriptions in dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1): ?v ol_f ?was ?fast, high level output voltage?; is ?fast, low level output voltage? ?v ol_sym ?was ?symmetric, high level output voltage?; is ?symmetric, low level output voltage? supply current (3.3 v, nvusro[pad3v5v] = 1): updated symbols main oscillator output electrical characteristics (5.0 v, nvusro[pad3v5v] = 0): replaced instances of extal with xtal main oscillator output electrical characteristics (3.3 v, nvusro[pad3v5v] = 1): replaced instances of extal with xtal fmpll electrical characteristics: replaced ?pllmrfm? with ?fmpll? in table title; updated conditions; removed f sys row; updated f fmpllout min value adc conversion characteristics: updated symbols; added row t adc_pu flash memory read access timing: added footnote to ?conditions? column section 3.16.1, pad ac specifications : added pad output delay diagram in the range of figures ?dspi classic spi timing ? master, cpha = 0? to ?dspi pcs strobe (pcss) timing?: added note updated order codes updated ?commercial product code structure? figure table 45 : added abbreviations ?dut?, ?npn?, and ?rbw? table 46. revision history (continued) date revision changes spc560p44lx, spc560p50lx revision history doc id 14723 rev 9 111/112 18-jul-2012 8 updated table 1 (device summary) section 1.5.4, flash memory : changed ?data flash memory: 32-bit ecc? to ?data flash memory: 64-bit ecc? figure 40 (commercial product code structure) , replaced "c = 60 mhz, 5 v" and "d = 60 mhz, 3.3 v" with respectively "c = 40 mhz, 5 v" and "d = 40 mhz, 3.3 v" table 9 (absolute maximum ratings) , updated tv dd parameter, the minimum value to 3.0 v/s and the maximum value to 0.5 v/s table 7 (pin muxing) , changed the description in the column "i/o direction" from "i/o" to "o" for the following port pins: a[10] with function b[0] a[11] with function a[0] a[11] with function a[2] a[12] with function a[2] a[12] with function b[2] a[13] with function b[2] c[7] with function a[1] c[10] with function a[3] c[15] with function a[1] d[0] with function b[1] d[10] with function a[0] d[11] with function b[0] d[13] with function a[1] d[14] with function b[1] updated section 3.8.1, voltage regulator electrical characteristics added table 27 (i/o consumption) section 3.10, dc electrical characteristics : deleted references to ?oscillator margin? deleted subsection ?nvusro[oscillator_margin] field description? table 21 (dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0)) , added ipu row for reset pin table 23 (dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1)) , added ipu row for reset pin table 33 (adc conversion characteristics) , added v inan entry removed ?order codes? table figure 40 (commercial product code structure) : added a footnote updated ?e = data flash memory? 18-sep-2013 9 updated disclaimer table 46. revision history (continued) date revision changes spc560p44lx, spc560p50lx 112/112 doc id 14723 rev 9 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com |
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